CS8401A-CS Cirrus Logic, Inc., CS8401A-CS Datasheet
CS8401A-CS
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CS8401A-CS Summary of contents
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... The audio serial port is double buffered and capable of sup- porting a wide variety of formats. The CS8401A has a configurable internal buffer memo- ry, loaded via a parallel port, which may be used to buffer channel status, auxiliary data, and/or user data. ...
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... Note 1 Symbol Note 2 CS8401/2A-IP or -IS Note for ’IP’ & ’IS’; VD Symbol ( 200 3.2mA) CS8401A Note 4 CS8402A Note 4 CS8401/2A CS8401A CS8402A Symbol Min Max VD+ 6 IND -0.3 VD -55 125 T stg ...
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... DIGITAL CHARACTERISTICS - RS422 DRIVERS (TXP, TXN pins only; VD 10%) Parameter Output High Voltage Output Low Voltage SWITCHING CHARACTERISTICS - CS8401A PARALLEL PORT ( for suffixes ’-CP’ and ’-CS’ Parameter ADDRESS valid to CS low CS high to ADDRESS invalid RD/WR valid to CS low ...
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... The diagrams show SBC rising coincident with the first rising edge of SCK after FSYNC transitions. This is true for all modes except FSF0 & 1 both equal 1 in the CS8401A, and format 4 in the CS8402A. In these modes SBC is delayed one full SCK period. ...
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... SCK t t sss ssh SDATA t t css sch C,U uss suh SBC External +5V Clock MCK 7 FSYNC 6 SCK 8 SDATA 15 INT CS8401A RD/ Figure 1. CS8401A Typical Connection Diagram CS8401A CS8402A t sckf +5V 19 VD+ 0 GND 20 TXP Transmitter Circuit 17 See Appendix B TXN 5 ...
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... MCK VD+ FSYNC 6 GND SCK 8 SDATA SBF M1 CS8402A SBC TXP 16 RST TXN 8 Dedicated C.S. Bits CS8401A CS8402A 0 Serial Port Mode Select 21 20 Transmitter Circuit 17 See Appendix B 0 Serial Port Mode Select 21 20 Transmitter Circuit 17 See Appendix B ...
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... If RD/WR is high, the value in the buffer memory, at the specified address, is placed on the data bus. The detailed timing for reading and writing the CS8401A can be found in the Digital Switching Characteristics table. The memory space is allocated as shown in Figure 5. There are three defined buffer memory modes select- able by two bits in control register 2 ...
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... In Transparent Mode (TRNPT = "1") the MCK, FSYNC, SCK and SDATA inputs of the CS8401A can be connected to their corresponding outputs of the CS8411. In Trans- parent Mode, FSYNC synchronizes the transmitter and the receiver. The data delay through the CS8401A ...
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... Memory Mode Figure 5. CS8401A Buffer Memory Modes DS60F1 X:00 FLAG2: High for first four bytes of channel status FLAG1: Memory mode dependent - See figure 11 FLAG0: High for last two bytes of user data. X:01 BKST: Causes realignment of data block when set to "1". ...
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... When RST is low, the differential line drivers are set to ground and the block counters are reset to the beginning of the first block. In order to properly synchronize the rest of the CS8401A to the audio serial port, the transmit timing counters, which in- clude the flags in the status register, are not enabled ...
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... FSYNC Output 11 1 FSYNC Output Figure 10. CS8401A Serial Port SDATA and FSYNC Timing MSB last mode restricting the number of SCK periods between samples to the sample word length. The 16-, 18-, and 20-bit LSB-last modes require at least 16, 18 SCK periods per sample respectively master, 32 SCK pe- riods are output per sample ...
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... Channel Status Byte (Expanded (Expanded) Sub-frame 7 8 LSB Audio Data Figure 11. CS8401A Status Register Flag Timing CS8401A MSB Validity User Data Channel Status Data ...
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... User Address Figure 12. CS8401A Buffer Memory Read Sequence - MODE 0 DS60F1 reads this buffer in a cyclic non-destructive man- ner and stores the byte in an 8-bit shift register that is shifted once per two transmitted audio samples (once per frame). Flag 1 in the status register can be used to moni- tor the channel status buffer ...
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... Aux. Address 10 13, Figure 13. CS8401A Buffer Memory Read Sequence - MODE 1 14 buffer; however, four auxiliary data bits are transmitted per audio sample (sub-frame). Since the auxiliary buffer must be read four times as often as the user data buffer and is four times as large, flag 0 can be used to monitor both. ...
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... User Address Figure 14. CS8401A Buffer Memory Read Sequence - MODE 2 Buffer-Read and Interrupt Timing As mentioned previously in the buffer mode sec- tions, conflicts between externally writing to the buffer ram and the CS8401A internally reading bytes of ram for transmission may be averted by using the flag levels to avoid the section cur- rently being addressed by the part ...
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... GND 7 18 SDATA TXN RD/ INT CS8401A DATA BUS BIT 3 DATA BUS BIT 2 DATA BUS BIT 1 DATA BUS BIT 0 TRANSMIT POSITIVE POWER GROUND TRANSMIT NEGATIVE READ/WRITE SELECT INTERRUPT CHIP SELECT ADDRESS BUS BIT 0 DS60F1 ...
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... Clock input which defines the transmit timing. It can be configured, via control register 2, for 128, 192, 256, or 384 times the sample rate. TXP, TXN - Differential Line Drivers, PINS 20, 17. RS422 compatible line drivers. Drivers are pulled low when part is in reset state. DS60F1 CS8401A resistor to 17 ...
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CS8402A DESCRIPTION The CS8402A accepts 16- to 24-bit audio samples through a serial port configured in one of seven for- mats; provides several pins dedicated to particular channel status bits; and allows all channel status, user, and validity bits to ...
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FORMAT 0: FSYNC (out) SCK (out) SDATA (in) FORMAT 1: FSYNC (in) SCK (in) SDATA (in) FORMAT 2: FSYNC (in) SCK (in) SDATA (in) FORMAT 3: (RESERVED) FORMAT 4: FSYNC (in) SCK (in) SDATA (in) FORMAT 5: FSYNC (in) SCK ...
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Serial Port The serial input pins for channel status (C), user (U), and validity (V) are sampled during the first bit period after the active edge of FSYNC for all formats except Format 4, which is sampled ...
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This sub-frame contains channel status byte 0, bit 0. CBL returns low one bit period be- fore the start of the frame that contains bit 0 of channel status byte 16. CBL is the exact inverse of flag 1 ...
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When FSYNC is a word clock (Format 2), CBL is sampled when left C,U,V are sampled. When FSYNC is Left/Right, CBL is sampled when left C,U,V are sampled. The channel status block boundary is reset when CBL transitions from low ...
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C2 is tied high, channel status bit 2 will be trans- mitted as a zero. Also, FC0 and FC1 are encoded versions of channel status bits 24 and 25, which define the sample frequency. When FC0 and FC1 are both ...
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SDATA 6 SCK 7 FSYNC 10 SBF SBC Register PRO FC0 FC1 C2 C3 Figure 21. CS8402A Block Diagram - Consumer Mode, CD Submode SBF U SBC Data latched ...
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PIN DESCRIPTIONS CS BIT BIT 3 PROFESSIONAL MODE CS BIT 1 / FREQ. CTRL BIT BIT 2 MASTER CLOCK SERIAL DATA CLOCK FRAME SYNC SERIAL INPUT DATA VALIDITY INPUT CS SERIAL IN ...
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V - Validity, PIN 9. Validity bit serial input port. This bit is defined according to the digital audio standards wherein signifies the audio signal is suitable for conversion to analog signifies the audio ...
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TRNPT/FC1 - Transparent Mode / Frequency Control 1, PIN 24. In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting TRNPT high, allows the CS8402A to be connected directly to a CS8412. In transparent mode, ...
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... Appendix A: RS422 Driver Information The RS422 drivers on the CS8401A and CS8402A are designed to drive both the professional and con- sumer interfaces. The AES/EBU specification for professional/broadcast use calls for a 110 impedance and a balanced drive capability. Since the transmitter impedance is very low, a 110 should be placed in series with one of the transmit pins ...
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... R1. PLD is an internal signal that parallel loads R1 into the R2 buffer, and, at the same time, the C, U, and V bits are latched. On the CS8401A, the C, U, and V bits are held in RAM, whereas on the CS8402A, they are latched from external pins. The PLD signal rises on the first SCK edge that can latch data ...
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... RST, the part synchronizes the audio port to IMCK as shown in Figure B2. Since PLD is based on FSYNC and LDS is based on IMCK, if Ordering Guide Model CS8401A-CP CS8401A-IP CS8401A-CS CS8401A-IS CS8402A-CP CS8402A-IP CS8402A-CS CS8402A-IS * Although the ’-CP’ and ’-CS’ suffixed parts are guaranteed to operate over they are tested only. If testing over temperature is desired, the ’ ...
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D SEATING PLANE e1 B1 NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN ...
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Notes • ...
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