UPD30121F1-131-GA1 NEC, UPD30121F1-131-GA1 Datasheet
UPD30121F1-131-GA1
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UPD30121F1-131-GA1 Summary of contents
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... PD30121F1-168-GA1 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14691EJ1V0DS00 (1st edition) ...
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PIN CONFIGURATION 224-pin plastic FBGA (16 16) PD30121F1-131-GA1 PD30121F1-168-GA1 Bottom view Top view ...
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Pin No. Power Pin Name Supply A1 3 C15 DD A2 3.3 V SHB# C16 A3 3.3 V BUSCLK C17 A4 3.3 V HLDACK# C18 A5 3.3 V IOCHRDY D1 A6 3.3 V MEMW 3.3 ...
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Pin No. Power Pin Name Supply P17 3.3 V CLKX2 T6 P18 2.5 V GND2 (GNDPD 3.3 V ADD1 T8 R2 3.3 V POWER T9 R3 3.3 V GND3 T10 R4 3.3 V GND3 T11 R5 3.3 V ...
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PIN IDENTIFICATION ADD (0:25): Address Bus ADIN (0:2): General Purpose Input for A/D AFERST#: AFE Reset AGND: GND for A/D AUDIOIN: Audio Input AUDIOOUT: Audio Output for A BATTINH: Battery Inhibit BATTINT#: Battery Interrupt Request ...
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... INTERNAL BLOCK DIAGRAM AND EXAMPLE OF CONNECTION OF EXTERNAL BLOCKS 32.768 kHz 18.432 MHz OSB LCD module PD16661 LCD panel 480 240 PC card PCMCIA /buffer ROM/SROM/flash memory EDO DRAM/ SDRAM V 4121 R CPU CORE INTERNAL BLOCK DIAGRAM Virtual address bus Internal data bus Bus ...
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... PIN FUNCTIONS.................................................................................................................................. 8 1.1 Pin Functions .............................................................................................................................................8 1.2 Pin Status in Specific Status...................................................................................................................17 1.3 Recommended Connection and I/O Circuit Types................................................................................21 1.4 Pin I/O Circuits .........................................................................................................................................24 2. ELECTRICAL SPECIFICATIONS...................................................................................................... 25 3. PACKAGE DRAWING ....................................................................................................................... 71 4. RECOMMENDED SOLERING CONDITIONS .................................................................................. 72 CONTENTS Data Sheet U14691EJ1V0DS00 PD30121 7 ...
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... DBUS32 signal = 0> When accessing DRAM (EDO type): This is the DRAM's RAS signal (MRAS3#). This signal is active when a valid row address is output via the ADD bus for the DRAM connected to the high-order address. When accessing SDRAM: This is the SDRAM's chip select signal (CS3#). This signal is active when a command is issued for the SDRAM connected to the high-order address ...
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... DBUS32 signal = 0> When accessing DRAM (EDO type): This is the DRAM's RAS signal (MRAS2#). This signal is active when a valid row address is output via the ADD bus for the DRAM connected to the next highest address after the highest high-order address. When accessing SDRAM: This is the SDRAM's chip select signal (CS2#). This signal is active when a command is issued for the SDRAM connected to the second highest high-order address ...
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... This is the 18.432-MHz oscillator’s input pin connected to one side of a crystal resonator. CLKX2 O This is the 18.432-MHz oscillator’s output pin connected to one side of a crystal resonator. FIRCLK I This is the 48-MHz clock input pin. Fix this at high level when FIR is not used. ...
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Battery monitor interface signals Signal I/O BATTINH/ I This function differs depending on how the MPOWER signal is set. BATTINT# <When MPOWER signal = 0> BATTINH function This signal enables/prohibits activation due to power-on Enable activation 0 ...
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RS-232C interface signals Signal I/O RxD I This is a receive data signal used when the RS-232C controller sends serial data to the V CTS# I This is a transmit enable signal. Assert this signal when the ...
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IrDA interface signals Signal I/O IRDIN I This is an IrDA serial data input signal used when the V controller, for both FIR and SIR. If the IrDA controller used product, however, this signal ...
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Touch panel/general purpose A/D interface signals Signal I/O TPX (0:1) I/O This is an I/O signal that is used for the touch panel. It uses the voltage applied to the X coordinate and the voltage input to the Y ...
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LED interface signal Signal I/O LEDOUT# O This is an output signal for lighting LEDs. (14) Initial setting signals Signal Name I/O DBUS32/ I/O The function differs depending on the operating status. GPIO48 <During normal operation (output)> This can ...
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Dedicated V and GND signals DD Signal Name Power-Supply System GNDP 2 2 GNDPD 2 3 CGND 3 3 DGND 3.3 ...
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Pin Status in Specific Status Pin Name After Reset by After Reset by the the RTC Reset Deadman’s Switch or RSTSW# Signal ADD25/SCLK 0 ADD (0:24) 0 DATA (0:15) 0 DATA (16:31)/ 0/ Hi-Z GPIO (16:31) LCDCS# Hi-Z RD# ...
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Pin Name After Reset by After Reset by the the RTC Reset Deadman’s Switch or RSTSW# Signal SHB# Hi-Z IOR# Hi-Z IOW# Hi-Z MEMR# Hi-Z MEMW# Hi-Z ZWS# RSTOUT Hi-Z IOCS16# MEMCS16# IOCHRDY HLDRQ# HLDACK# Hi-Z CKE 0 RTCX1 RTCX2 ...
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Pin Name After Reset by After Reset by the the RTC Reset Deadman’s Switch or RSTSW# Signal Note 1 DDIN / / GPIO45 Hi-Z Note 1 DDOUT / 1/ GPIO44 1 Note 1 DRTS GPIO46 1 Note 1 ...
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Pin Name After Reset by After Reset by the the RTC Reset Deadman’s Switch or RSTSW# Signal IRING ILCSENSE Note 1 OFFHOOK Hi-Z Note 1 MUTE Hi-Z Note 1 AFERST# 0 SDI FS SDO 0 HSPSCLK Note 1 TELCON Hi-Z ...
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... When used as the RAS signal of extended DRAM, external pull-up is recommended for the V 5. When the MPOWER pin outputs the low-level, intermediate-level input is enabled. Remarks 1. No specification ( ) in the External Processing column indicates that the external processing is unnecessary specification ( ) in the Recommended Connection of Unused Pins column indicates that the pin is always connected. External Drive ...
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... DCTS#/GPIO47 Note Intermediate-level input is enabled when the MPOWER pin is set for low-level output. Remarks 1. No specification ( ) in the External Processing column indicates that the external processing is unnecessary specification ( ) in the Recommended Connection of Unused Pins column indicates that the pin is always connected. 22 External ...
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... Pull up/Pull down SMODE2 Pull up/Pull down Notes 1. Connect an operation amplifier which has high-impedance input characteristics, since the output level of AUDIOOUT pin varies according to the external impedance internal pull-up or pull-down resistors are used in GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14) pins switch between pull up, pull down, and open by software ...
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... Remarks 1. No specification ( ) in the External Processing column indicates that the external processing is unnecessary specification ( ) in the Recommended Connection of Unused Pins column indicates that the pin is always connected. 1.4 Pin I/O Circuits Type A V Data P-ch Output N-ch disable Input enable Type B Pullup enable V Data P-ch Open drain ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Supply voltage V 2 DD2 V 3.3 V (CV DD3 Input voltage DD3 V DD3 Storage temperature T stg Cautions 1. Do ...
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Operating Conditions (1) 131 MHz model Parameter Symbol Supply voltage V DD2 V DD3 Ambient temperature T A Note 1 Oscillation start voltage V DDS Note 2 Oscillation hold voltage V DDH1 Note 3 Oscillation hold voltage V DDH2 Notes ...
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DC Characteristics (1) 131 MHz model ( + Parameter Symbol Output voltage, high V OH1 Note 1 Output voltage, high V OH2 Output voltage, low V OL1 Note 1 Output voltage, low V OL2 ...
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Parameter Symbol Note 2 Power supply current I In Fullspeed mode DD2 In Standby mode In Suspend mode In Hibernate mode, V when LED unit is off. Note Fullspeed mode, ADD (0:24), DD3 ADD25/SCLK, CKE, RD#, WR#, ...
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MHz model ( + Parameter Symbol Output voltage, high V OH1 Note 1 Output voltage, high V OH2 Output voltage, low V OL1 Note 1 Output voltage, low V OL2 Note 2 ...
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Parameter Symbol Note 2 Power supply current I In Fullspeed mode DD2 In Standby mode In Suspend mode In Hibernate mode, V when LED unit is off. Note Fullspeed mode, ADD (0:24), DD3 ADD25/SCLK, CKE, RD#, WR#, ...
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Data Retention Characteristics ( Parameter Note 1 Data retention voltage Note 2 Data retention input voltage, high Notes 1. The data retention voltage is the voltage at which the operation of the Elapsed Time timer and ...
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AC Characteristics (131 MHz model: T 168 MHz model test input waveform (a) CTS#, DATA (0:15), DATA (16:31)/GPIO (16:31), DBUS32/GPIO48, DCTS#/GPIO47, DDIN/GPIO45, DSR#, DTR#/CLKSEL0, FS, FIRDIN#/SEL, HLDRQ#, ILCSENSE, IOCHRDY, IOCS16#, IRDIN, LCDRDY, MEMCS16#, RxD, RTS#/CLKSEL1, SDI, SMODE1/GPIO49, SMODE2, ...
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Load condition (a) ADD (0:24), ADD25/SCLK, CKE, RD#, WR#, TPX (0:1), TPY (0:1) ADD (0:24), ADD25/SCLK, CKE, RD#, WR#, TPX (0:1), TPY (0:1) (b) Other output pins Output pin (other than those shown in (a)) DUT C = 120 pF ...
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Clock parameter (1/2) Parameter Symbol HSPSCLK high-level width t WHSH HSPSCLK low-level width t WHSL HSPSCLK clock frequency f HSCYC HSPSCLK clock cycle t CYHS HSPSCLK clock rise time t HSR HSPSCLK clock fall time t SHF HSPMCLK high-level ...
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Clock parameter (2/2) HSPSCLK (input) t HSR HSPMCLK (output) SCLK (output) BUSCLK (output) t CYHS t t WHSH WHSL t SHF t CYHM t t MPH MPL BCLKH1 BCLKL1 t t BCLKH2 BCLKL2 ...
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Reset parameter Parameter Symbol Reset input low-level width t WRSL RTCRST# (input) Remark For the RTCRST# characteristics at power application, refer to V (3) Initialization parameter Parameter Symbol Data sampling time t SS (from RTCRST# ) Output delay time ...
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GPIO interface parameter (1/2) Parameter Symbol Input level width t INP1 t INP2 t INP3 GPIO input rise time t GPINR1 t GPINR2 GPIO input fall time t GPINF1 t GPINF2 Output level width t OUTP Notes 1. Applied ...
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GPIO interface parameter (2/2) (a) Input level width Notes 1. GPIO (0:3) pins 2. GPIO (9:14), DCD#/GPIO15 pins 3. SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO8, DATA (16:31)/GPIO (16:31) pins (b) GPIO input rise/fall time t Note 1 GPINF1 t Note ...
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EDO-type DRAM read parameter (1/2) The target DRAM is the PD42S16165L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60, 42S65165G5-A50, or 42S65165G5-A60. Parameter MRAS (0:3)# pulse width MRAS (0:3)# hold time (from UCAS#/LCAS# precharge) MRAS (0:3)# precharge time UCAS#/LCAS# hold time (from MRAS (0:3)#) ...
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EDO-type DRAM read parameter (2/2) Note 1 MRAS (0:3)# (output) Note 2 UCAS#/LCAS# (output) t ASR ADD (19:23) (output) ADD (9:18) (output) RD# (output) Note 3 DATA Invalid (I/O) Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins ...
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EDO-type DRAM write parameter (1/2) The target DRAM is the PD42S16165L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60, 42S65165G5-A50, or 42S65165G5-A60. Parameter MRAS (0:3)# pulse width MRAS (0:3)# hold time (from UCAS#/LCAS# precharge) MRAS (0:3)# precharge time UCAS#/LCAS# hold time (from MRAS (0:3)# ...
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EDO-type DRAM write parameter (2/2) Note 1 MRAS (0:3)# (output) Note 2 UCAS#/LCAS# (output) t ASR ADD (19:23) (output) ADD (9:18) (output) WR# (output) Note 3 DATA Invalid (I/O) Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins ...
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DRAM refresh parameter The target DRAM is the PD42S161615L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60, 42S65165G5-A50, or 42S65165G5-A60. (a) CAS-before-RAS refresh parameter Parameter Read/write cycle time MRAS (0:3)# pulse width MRAS (0:3)# precharge time UCAS#/LCAS# setup time (to MRAS (0:3)# ) UCAS#/LCAS# ...
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CAS-before-RAS self-refresh parameter Parameter Note MRAS (0:3)# pulse width MRAS (0:3)# precharge time UCAS#/LCAS# hold time Note The CAS-before-RAS self-refresh parameter is valid when t Note 1 MRAS (0:3)# (output) Note 2 UCAS#/LCAS# (output) Notes 1. In 32-bit mode: ...
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Normal ROM parameter (1/2) Parameter Note Data access time (from address) Note Data access time (from ROMCS (0:3)# ) Note Data access time (from RD# ) Data input setup time Data input hold time Note The value of N ...
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Normal ROM parameter (2/2) When WROMA (0:2) bits = 111 ADD (19:23), ADD (0:8) (output) ADD (9:18) (output) ROMCS (0:3)# (output) RD# (output) Note DATA Invalid (I/O) Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) ...
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Page ROM parameter (1/2) Parameter Note Data access time (from address) Note Data access time (from ROMCS (0:3)# ) Note Data access time (from RD# ) Data input setup time Data input hold time Note The value of N ...
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Page ROM parameter (2/2) ADD (1:3) (output) ADD (4:23), ADD0 (output) ROMCS (0:3)# (output) RD# (output) Note DATA Invalid (I/O) Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins In 16-bit mode: Applied to DATA ...
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Flash memory mode write parameter Parameter Write cycle time Address setup time (to WR# ) Address setup time (to ROMCS (0:3)# ) ROMCS (0:3)# setup time (to WR# ) WR# low-level width ROMCS (0:3)# hold time (from WR# ) ...
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Flash memory mode read parameter Parameter Data output delay time from address Data output delay time from ROMCS (0:3)# Address setup time (to ROMCS (0:3)# ) Data output delay time from RD# Address setup time (to RD# ) ROMCS ...
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System bus parameter (IOCHRDY) (1/3) Parameter BUSCLK high-level width BUSCLK low-level width Address setup time (to BUSCLK) Notes 3, 4 Address setup time (to command signal ) Note 3 Command signal setup time (to BUSCLK) Notes 3, 4 Command ...
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System bus parameter (IOCHRDY) (2/3) When WISAA (0:2) bits = 010, BSEL bit = BCLKH1 BCLKL1 Note 1 BUSCLK (output) Note 1 BUSCLK (output) Note 1 BUSCLK (output) Note 1 BUSCLK (output) ADD (19:25), ADD (0:8) ...
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System bus parameter (IOCHRDY) (3/3) When WISAA (0:2) bits = 010, BSEL bit = BCLKH2 BCLKL2 BUSCLK (output) Note t AVCK ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) SHB# (output) MEMR#/MEMW#, IOR#/IOW# (output) IOCHRDY (input) ...
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System bus parameter (ZWS#) (1/2) Parameter Address setup time (to BUSCLK) Notes 1, 2 Address setup time (to command signal ) Note 1 Command signal setup time (to BUSCLK) Notes 1, 2 Command signal low-level width Note 1 Address ...
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System bus parameter (ZWS#) (2/2) When WISAA (0:2) bits = 101, BSEL bit = 0 Note 1 BUSCLK (output) Note 1 BUSCLK (output) Note 1 BUSCLK (output) Note 1 BUSCLK (output) ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) ...
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High-speed system bus parameter (IOCHRDY) (1/2) Parameter Notes 1, 2 Address setup time (to command signal ) Notes 1, 2 Command signal low-level width Note 1 Address hold time (from command signal ) Notes 1, 2 Command signal recovery ...
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High-speed system bus parameter (IOCHRDY) (2/2) When WISAA (2:0) bits = 111 ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) SHB# (output) LCDCS# (output) MEMR#/MEMW# (output) IOCHRDY (input) ZWS# (input) MEMCS16#, IOCS16# (input) DATA Invalid (output) DATA Invalid (input) ...
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High-speed system bus parameter (ZWS#) (1/2) Parameter Notes 1, 2 Address setup time (to command signal ) Notes 1, 2 Command signal low-level width Note 1 Address hold time (from command signal ) Notes 1, 2 Command signal recovery ...
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High-speed system bus parameter (ZWS#) (2/2) When WISAA (0:2) bits = 111 ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) SHB# (output) LCDCS# (output) MEMR#/MEMW# (output) IOCHRDY (input) ZWS# (input) MEMCS16#, IOCS16# (input) DATA Invalid (output) DATA Invalid (input) ...
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LCD interface parameter (1/2) Parameter Note 1 Address setup time (to command signal ) Note 1 Address hold time (from command signal ) Note 1 Command signal recovery time LCDRDY sampling start time Command signal delay time from LCDRDY ...
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LCD interface parameter (2/2) ADD (19:20), ADD (0:8) (output) ADD (9:18) (output) SHB# (output) LCDCS# (output) RD#/WR# (output) LCDRDY (input) DATA Invalid (output) DATA Invalid (input) Remark The broken lines indicate high impedance CLR RHCH ...
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Bus hold parameter (1/2) Parameter Symbol Note HLDRQ# input pulse width t FHP Data floating delay time t FOFF Data valid delay time t FON Note HLDRQ# input pulse width t SHP Data floating delay time t SOFF Data ...
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Bus hold parameter (2/2) (a) Bus hold in Fullspeed/Standby mode HLDRQ# (input) HLDACK# (output) Note 1 Note 2 BUSCLK (output) Notes 1. UUCAS#/MRAS3#, ULCAS#/MRAS2#, MRAS (0:1)#, UCAS#, LCAS# pins 2. SHB#, IOR#, IOW#, MEMR#, MEMW#, RD#, WR#, ADD (0:24), ...
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Keyboard Interface parameter (1/2) Parameter KSCAN (0:11) high-level width Idle time (KSCAN (n+1) from KSCANn ) Key scan interval time Key input setup time (to KSCANn ) Key input hold time (from KSCANn ) Notes 1. K: Sum of ...
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Keyboard Interface parameter (2/2) (c) Keyboard port parameter Hi-Z KSCANn (output) KPORT (0:7) (input) Remark Hi Data Sheet U14691EJ1V0DS00 PD30121 65 ...
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Serial interface parameter (1/2) Parameter Note TxD output pulse width Note RxD input pulse width Note IRDOUT# high-level output pulse width IRDIN input pulse width Note N: Data transfer rate per bit, which is determined by the divisor of ...
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Serial interface parameter (2/2) TxD (output) RxD (input) IRDOUT# (output) IRDIN (input) t TXD t RXD t IRDOUT t IRDIN Data Sheet U14691EJ1V0DS00 PD30121 67 ...
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Debug serial interface parameter Parameter Note DDOUT output pulse width Note DDIN input pulse width Note N: Transfer rate of baud rate per bit set to the BPR0 bits of the BPRM0REG register. BPR0 (2:0) Bits 111 110 101 ...
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SDRAM interface parameter Parameter SCLK clock cycle SCLK high-level width SCLK low-level width Data output delay time (from SCLK ) Address output delay time (from SCLK ) WR# output delay time (from SCLK ) Data input setup time Data ...
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... DNL Notes 1. Applied to AUDIOOUT pin. 2. Quantization error is excluded. Load Coefficient (Delay Time per Load Capacitance) Parameter Symbol Load coefficient CLD Caution Because NEC confirmed the characteristics by simulation at the design phase, screening on shipment is omitted – 2 DD2 = – ...
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PACKAGE DRAWING 224-PIN PLASTIC FBGA (16x16 Index mark ...
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... The PD30121 should be soldered and mounted under the following recommended conditions. For details of recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions ...
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Data Sheet U14691EJ1V0DS00 PD30121 73 ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability • Ordering information • ...
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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...