M66258FP MITSUBISHI, M66258FP Datasheet
M66258FP
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M66258FP Summary of contents
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... DESCRIPTION The M66258FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 8192 words x 8 bits. The M66258FP, performing reading and writing operations at different cycles independently and asynchronously, is optimal for buffer memory to be used between equipment of different data processing speeds ...
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... LINE MEMORY Read control circuit Read address counter Write address counter Write control circuit M66258FP ...
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... D0 WE, WRES, WCK GND I RE, RRES, RCK, – GND GND, output open 20ns WCK RCK f = 1MHz f = 1MHz M66258FP 8192 x 8-BIT LINE MEMORY Ratings Unit – -0.5 +6.0 V – -0 – -0 825 mW – -65 150 C Limits Min. ...
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... WE high-level period 8192 • high-level period 8192 • Perform reset operation after turning on power supply. 4 Parameter Parameter - WRES low-level period WCK - RRES low-level period RCK M66258FP 8192 x 8-BIT LINE MEMORY Limits Unit Min. Typ. Max ...
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... ODIS OEN RCK judged with 10% of the ODIS judged with ODIS HZ 1.3V t ODIS(HZ) 90% t ODIS(LZ) 10% M66258FP 8192 x 8-BIT LINE MEMORY V CC RL=1K SW1 SW2 CL = 5pF : t RL=1K Item SW1 t ODIS(LZ) Close t ODIS(HZ) Open t OEN(ZL) Close t OEN(ZH) Open 3V 1.3V GND ...
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... Dn 6 n+1 cycle n+2 cycle Disable cycle WCKH WCKL WEH NWES (n+1) (n+2) n cycle Reset cycle t NRESH RESS (n) M66258FP 8192 x 8-BIT LINE MEMORY n+3 cycle n+4 cycle t NWEH t WES (n+3) WRES = "H" 0 cycle 1 cycle 2 cycle t t RESH NRESS (0) ( "L" (n+4) (2) ...
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... The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well. M66258FP 8192 x 8-BIT LINE MEMORY n cycle ...
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... RCK RRES (n- n+2 cycle Disable cycle RCKL REH NRES t ODIS (n+1) (n+2) n cycle Reset cycle t NRESH RESS (n) (0) M66258FP 8192 x 8-BIT LINE MEMORY n+3 cycle n+4 cycle t NREH t RES OEN HIGH-Z (n+ RRES = "H" 0 cycle 1 cycle 2 cycle t t RESH NRESS t AC ...
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... ( cycle 8190 cycle 8191 cycle (2) (8189) (8190) (8191) 8192 cycle n-2 cycle n-1 cycle 2 cycle (n-3) (n-2) (1) (2) m cycle M66258FP 8192 x 8-BIT LINE MEMORY 8192 cycle 8193 cycle 8194 cycle (0') (1') (2 (0') (1') (2 (0) (1) (2) WE "L" n cycle ...
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... RESS RESH (1) (2) (n-2) (n-1) m cycle cycle n-1 cycle n cycle t t NREH RES (1) (2) (n-2) (n-1) m cycle t M66258FP 8192 x 8-BIT LINE MEMORY n+1 cycle n+2 cycle n+3 cycle (n) (n+1) (n+2) (n+ (0) (1) (2) (3) WE "L" n+1 cycle n+2 cycle n+3 cycle (n) (n+1) ...
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... Output cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other. n cycle <1>* WCK (n-1)<1>* (n)<1> cycle <0>* RCK Qn (n-1)<0>* (n)<0>* n+1 cycle n+2 cycle (n) (n+1) n-2 cycle n-1 cycle invalid 0 cycle <2>* (0)<2>* 0 cycle <1>* (0)<1>* MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY n+3 cycle (n+2) (n+3) n cycle (n) n cycle <2>* (n-1)<2>* (n)<2>* n cycle <1>* (n-1)<1>* (n)<1>* <0>*, <1>* and <2>* indicate value of lines. 11 ...
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... M66258 line delay Main scan direction Sub Scan Resolution Compensation Circuit with Laplacean Filter N n line image data (n+1) line Q7 image data (n-1) line n line (n+1) line M66258FP 8192 x 8-BIT LINE MEMORY Compensated image data N'=N+K { (N-A) + (N-B) } =N+K { (2N - (A+ Laplacean coefficient ...