PDI1394L11BA Philips Semiconductors, PDI1394L11BA Datasheet
PDI1394L11BA
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PDI1394L11BA Summary of contents
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PDI1394L11 1394 AV link layer controller Product specification INTEGRATED CIRCUITS 1997 Oct 21 ...
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... Digital Interface for Consumer Electronics Interface to any IEEE 1394–1995 Physical Layer Interface 5V Tolerant I/Os Single 3.3V supply voltage 2.0 DESCRIPTION The PDI1394L11, Philips Semiconductors 1394 Audio/Video (AV) Link Layer Controller IEEE 1394–1995 compliant link layer controller featuring an embedded AV layer interface. The AV layer is 3.0 QUICK REFERENCE DATA GND = 0V; T ...
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... Philips Semiconductors 1394 AV link layer controller 6.0 FUNCTIONAL DIAGRAM HIF A[8:0] HIF D[7:0] HIF WR_N HIF RD_N HIF CS_N HIF INT_N RESET_N CYCLEIN CYCLEOUT AV D[7:0] AVCLK AVVALID AVSYNC AVFSYNCIN AVFSYNCOUT AVENDPCK AVERR[1:0] 7.0 INTERNAL BLOCK DIAGRAM AV D[7:0] AVCLK AVSYNC AV LAYER AVVALID TRANSMITTER AFSYNCIN AND RECEIVER AVFSYNCOUT AVENDPCK ...
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... Philips Semiconductors 1394 AV link layer controller 8.0 APPLICATION DIAGRAM MPEG OR DVC INTERFACE DECODER DATA 8/ ADDRESS 9/ INTERRUPT & CONTROL HOST CONTROLLER 9.0 PIN DESCRIPTION 9.1 Host Interface PIN No. PIN SYMBOL I/O 14, 15, 16, 17, HIF A[8:0] I 18, 19, 20, 21 HIF D[7:0] I HIF WR_N I 27 HIF RD_N ...
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... Philips Semiconductors 1394 AV link layer controller 9.2 AV Interface PIN No. PIN SYMBOL I/O 77, 76, 75, 74, AV D[7:0] I/O 71, 70, 69 AVCLK I 57 AVSYNC I/O 59 AVFSYNCIN I 60 AVFSYNCOUT O 56 AVENDPCK I 61 AVVALID I/O 53 AVERR0 O 52 AVERR1 O 9.3 Phy Interface PIN No. PIN SYMBOL I/O 34, 35, 36, 37, PHY D[0:7] I/O 40, 41, 42, 43 46, 47 PHY CTL[0:1] ...
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... Philips Semiconductors 1394 AV link layer controller 10.0 RECOMMENDED OPERATING CONDITIONS SYMBOL SYMBOL PARAMETER PARAMETER V DC supply voltage CC V Input voltage I V High-level input voltage IH V Low-level input voltage IL I High-level output current OH I Low-level output current OL dT/dV Input transition rise or fall time T Operating ambient temperature range ...
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... Philips Semiconductors 1394 AV link layer controller 11.1 Buffer Memory Sizes Asynchronous Receive Transaction Response FIFO Asynchronous Receive Transaction Request FIFO Asynchronous Transmit Transaction Response FIFO Asynchronous Transmit Transaction Request FIFO AV Transmit/Receive Buffer 12.0 FUNCTIONAL DESCRIPTION 12.1 Overview The PDI1394L11 is an IEEE 1394–1995 compliant link layer controller. It provides a direct interface between a 1394 bus and various MPEG– ...
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... Philips Semiconductors 1394 AV link layer controller bytes rather than quadlets the address spaces is 256 bytes, requiring 8 address lines. The use bit interface introduces an inherent problem that must be solved: register fields can be more than 8 bits wide and be used (control) or changed (status) at every internal clock tick. If such ...
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... Philips Semiconductors 1394 AV link layer controller 12.3.2 Write accesses To write to an internal register the host interface must collect the 4 byte values into a 32 bit value and then write the result to the target register in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is ready to be written to the actual target register ...
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... Philips Semiconductors 1394 AV link layer controller 12.3.3 Byte order The bytes in each quadlet are numbered 0..3 from left (most significant) to right (least significant) as shown in Figure 1. To access a register at internal address N the CPU should use addresses access the upper 8 bits of the register. ...
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... Philips Semiconductors 1394 AV link layer controller HIF CS_N HIF RD_N T AS HIF WR_N HIF A8 HIF A0..HIF A7 T ACC HIF D0..HIF D7 RSR Figure 2. Read cycle signal timing (2 independent read cycles) HIF CS_N HIF RD_N HIF WR_N T AS HIF A0..HIF A8 <VALID ADDRESS> <WRITE DATA> ...
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... Philips Semiconductors 1394 AV link layer controller 12.5 Link Packet Data Formats The data formats for transmission and reception of data are shown below. The transmit format describes the expected organization for data presented to the link at the asynchronous transmit, physical response, or isochronous transmit FIFO interfaces. ...
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... Philips Semiconductors 1394 AV link layer controller Figure 5. Quadlet/Block Write Response Packet Transmit Format Table 1. No-Data Transmit Format Field Name spd This field indicates the speed at which this packet sent. 00=100 Mbs, 01=200 Mbs, and 10=400 Mbs. ...
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... Philips Semiconductors 1394 AV link layer controller Figure 7. Quadlet Read Response Transmit Format Table 2 ...
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... Philips Semiconductors 1394 AV link layer controller 12.5.1.3 Block Transmit The block transmit format is shown below, this is the generic format for reads and writes. The first quadlet contains packet control information. The second and third quadlets contain the 16-bit destination node ID and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses) ...
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... Philips Semiconductors 1394 AV link layer controller Table 3. Block Transmit Field Field Name spd, tLabel, rt, tCode, destinationID, destinationOffsetHigh, destinationOffsetLow, rCode dataLength extendedTcode block data padding 12.5.1.4 Unformatted Transmit The unformatted transmit format is shown in Figure 11. The first quadlet contains packet control information. The remaining quadlets contain data that is transmitted without any formatting on the bus ...
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... Philips Semiconductors 1394 AV link layer controller Table 5. Asynchronous Receive Fields Field Name destinationID This field is the concatenation of busNumbers (or all ones for “local bus”) and nodeNumbers (or all ones for broadcast) for this node. tLabel This field is the transaction label, which is used to pair up a response packet with its corresponding request packet. ...
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... Philips Semiconductors 1394 AV link layer controller 12.5.2.1 No-Data Receive The no-data receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlet contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for responses) ...
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... Philips Semiconductors 1394 AV link layer controller Figure 14. Quadlet Write Request Receive Format Figure 15 ...
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... Philips Semiconductors 1394 AV link layer controller 12.5.2.3 Block receive The block receive format is shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit sourceID and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses) ...
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... Philips Semiconductors 1394 AV link layer controller Figure 18. Block Read or Lock Response Receive Format 12.5.2.4 Self-ID and PHY packets receive The self-ID and PHY packet receive formats are shown below. The first quadlet contains a synthesized packet header with a tCode of 0xE (hex) ...
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... Philips Semiconductors 1394 AV link layer controller For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified and is not included ...
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... Philips Semiconductors 1394 AV link layer controller 12.5.3.1 Determining and Clearing Interrupts When responding to an interrupt event generated by the PDI1394L11, or operating in polled mode, the first register examined is the GLOBCSR register. The least significant nibble contains interrupt status bits from general sections of the device; the link layer controller, the AV transmitter, the AV receiver, and the asynchronous transceiver ...
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... Philips Semiconductors 1394 AV link layer controller 13.0 REGISTER MAP Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the lower 8 bits, and leave the other bits unaffected (see Section 12.3.2 for more information). The values written to undefined fields/bits are ignored and thus DON’ ...
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... Philips Semiconductors 1394 AV link layer controller 31 REGISTER ADDRESS IDREG BUS ID 0x000 LNKCTL BSYCTRL 0x004 LNKPHYINTACK 0x008 LNKPHYINTE 0x00C CYCLE_SECONDS CYCTM 0x010 PHYACS PHYRGAD 0x014 GLOBCSR 0x018 <RESERVED> 0x01C ITXPKCTL 0x020 0 ITXHQ1 0x024 ITXHQ2 FMT 0x028 ...
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... Philips Semiconductors 1394 AV link layer controller 31 REGISTER ADDRESS ITXCTL 0x034 ITXMEM 0x038 <RESERVED> 0x03C IRXPKCTL 0x040 IRXHQ1 SID 0x044 IRXHQ2 FMT 0x048 IRXINTACK 0x04C IRXINTE 0x050 IRXCTL 0x054 IRXMEM 0x058 <RESERVED> 0x05C . . . <RESERVED> 0x07C 1997 Oct TAG CHANNEL ...
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... Philips Semiconductors 1394 AV link layer controller 31 REGISTER ADDRESS ASYCTL 0x080 ASYMEM 0x084 TX_RQ_NEXT 0x088 TX_RQ_LAST 0x08C TX_RP_NEXT 0x090 TX_RP_LAST 0x094 RREQ 0x098 RRSP 0x09C ASYINTACK 0x0A0 ASYINTE 0x0A4 <RESERVED> 0x0A8 . . . <RESERVED> 0x0F8 1997 Oct MAXRC TOS ...
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... Philips Semiconductors 1394 AV link layer controller 13.1 Link Control Registers ID Register (IDREG) – Base Address: 0x000 13.1.1 The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset. 3130 ...
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... Philips Semiconductors 1394 AV link layer controller Bit 10: R/W Cycle Source: When asserted, the cycle_count field increments and the cycle_offset field resets for each positive transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field rolls over. Bit 9: R/W Cycle Timer Enable: When asserted, the cycle offset field increments. ...
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... Philips Semiconductors 1394 AV link layer controller 13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’ to the bit corresponding to the interrupt desired. This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the bits enables that function to create an interrupt ...
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... Philips Semiconductors 1394 AV link layer controller 13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018 This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the appropriate section of the device are cleared or disabled ...
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... Philips Semiconductors 1394 AV link layer controller Bit 3..2: R/W PM: packing mode variable sized bus packets, most generic mode fixed size bus packets MPEG–2 packing mode data, just CIP headers are transmitted. Bit 1: R/W EN_FS:enable generation/insertion of SYT stamps (Time Stamps) in CIP header. Bit 0: R/W Reset Isochronous Transmitter: causes transmitter to be reset when ‘ ...
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... Philips Semiconductors 1394 AV link layer controller 13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter. Bits 2, 3, and 4 ”auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to clear these interrupts to be alerted the next time ...
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... Philips Semiconductors 1394 AV link layer controller 13.2.7 Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038 The AV Transmitter Memory Status register reports on the condition of the internal memory buffer used to store incoming AV data streams before transmission over the 1394 bus. 3130 ...
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... Philips Semiconductors 1394 AV link layer controller Bit 10: R SPH: Indicates that a CYCTM based time stamp is inserted before each application packet (25 bits specified in the IEC 61883 International Standard). 13.2.10 Common Isochronous Receiver Packet Header Quadlet 2 (IRXHQ2) – Base Address: 0x048 Reset Value 0x0000FFFF Bit 31 ...
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... Philips Semiconductors 1394 AV link layer controller 13.2.13 Isochronous Receiver Control Register (IRXCTL) – Base Address: 0x054 Reset Value 0x00000000 Bit 17..16: R SPD: Speed of last received isochronous packet (S100 .. S400). ...
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... Philips Semiconductors 1394 AV link layer controller 13.3 Asynchronous Control and Status Interface 13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080 Reset Value 0x00300320 Bit 22: R/W ARXRST: Asynchronous receiver reset. This bit will auto clear when the link layer state machine is idle. ...
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... Philips Semiconductors 1394 AV link layer controller 13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088 Bit 31..0: W TX_RQ_NEXT: First/middle quadlet of packet for transmitter request queue (write only). ...
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... Philips Semiconductors 1394 AV link layer controller 13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098 3130 Reset Value 0x00000000 Bit 31..0: R RREQ:Quadlet of packet from receiver request queue (transfer register). ...
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... Philips Semiconductors 1394 AV link layer controller Bit 2: R/W TREQQWRERR: Transmitter request queue write error (transfer error). Bit 1: R/W TRSPQWR: Transmitter response queue written (transfer register emptied). Bit 0: R/W TREQQWR: Transmitter request queue written (transfer register emptied). 13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4 ...
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... Philips Semiconductors 1394 AV link layer controller 14.1 Pin Categories Table 11. Pin Categories Category 1: Category 2: Category 3: Input/Output Input Input HIF D[7:0] HIF A[8:0] RESET_N AVSYNC HIF CS_N CYCLEIN AVVALID HIF WR_N AVCLK AV D[7:0] HIF RD_N ISO_N AVFSYNCIN AVENDPCK 15.0 AC CHARACTERISTICS GND = 0V 50pF L SYMBOL PARAMETER t AV clock period ...
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... Philips Semiconductors 1394 AV link layer controller 16.0 TIMING DIAGRAMS 16.1 AV Interface Operation AVCLK MESSAGE AV D[7:0] AVSYNC AVVALID AVERR[0] ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR AVERR[1] 16.2 AV Interface Critical Timings AVCLK É É É [7:0], AVVALID, É É É VALID AVSYNC, AVENDPCK É É É ...
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... Philips Semiconductors 1394 AV link layer controller 16.3 PHY-Link Interface Critical Timings SCLK PHY D[0:7], PHY CTL[0:1] Figure 26. PHY D[0:7], PHY CTL[0:1] Input Setup and Hold Timing Waveforms PHY D[0:7], PHY CTL[0:1], LREQ Figure 27. PHY D[0:7], PHY CTL[0:1], and LREQ Output-Delay Timing Waveforms 16.4 Host Interface Critical Timings ...
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... Philips Semiconductors 1394 AV link layer controller 16.5 CYCLEIN/CYCLEOUT Timings CYCLEIN SCLK CYCLEIN CYCLEOUT 16.6 RESET Timings RESET_N 1997 Oct 21 50% 50% 50 CWH CWL t CP Figure 29. CYCLEIN Waveform 50 50% Figure 30. CYCLEOUT Waveforms 50% 50% t RESET Figure 31. RESET_N Waveform 44 Product specification PDI1394L11 SV00696 50% ...
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... Philips Semiconductors 1394 AV link layer controller QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 2.8 mm 1997 Oct 21 45 Product specification PDI1394L11 SOT318-2 ...
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... Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. ...