HY57V64820HGTP-H Hynix Semiconductor, HY57V64820HGTP-H Datasheet

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HY57V64820HGTP-H

Manufacturer Part Number
HY57V64820HGTP-H
Description
HY57V64820HGTP-H4 Banks x 2M x 8Bit Synchronous DRAM
Manufacturer
Hynix Semiconductor
Datasheet
DESCRIPTION
The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8.
HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
ORDERING INFORMATION
Note) Hynix supports lead free part for each speed grade with same specification.
This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.1/ Nov. 03
HY57V64820HGLTP-5/55/6/7
HY57V64820HGTP-5/55/6/7
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by DQM
Internal four banks operation
HY57V64820HGLTP-K
HY57V64820HGLTP-H
HY57V64820HGLTP-P
HY57V64820HGLTP-S
HY57V64820HGLTP-8
HY57V64820HGTP-K
HY57V64820HGTP-H
HY57V64820HGTP-P
HY57V64820HGTP-S
HY57V64820HGTP-8
Part No.
200/183/166/143MHz
200/183/166/143MHz
Clock Frequency
133MHz
133MHz
125MHz
100MHz
100MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Low power
Power
Normal
4 Banks x 2M x 8Bit Synchronous DRAM
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
Programmable CAS Latency ; 2, 3 Clocks
4Banks x 2Mbits x8
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Organization
Interface
HY57V64820HGTP
LVTTL
400mil 54pin TSOP II
Package
(Pb free)
1

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HY57V64820HGTP-H Summary of contents

Page 1

... Data mask function by DQM • Internal four banks operation ORDERING INFORMATION Part No. Clock Frequency HY57V64820HGTP-5/55/6/7 200/183/166/143MHz HY57V64820HGTP-K HY57V64820HGTP-H HY57V64820HGTP-8 HY57V64820HGTP-P HY57V64820HGTP-S HY57V64820HGLTP-5/55/6/7 200/183/166/143MHz HY57V64820HGLTP-K HY57V64820HGLTP-H HY57V64820HGLTP-8 HY57V64820HGLTP-P HY57V64820HGLTP-S Note) Hynix supports lead free part for each speed grade with same specification. ...

Page 2

... RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection HY57V64820HGTP DQ7 52 ...

Page 3

... Rev. 0.1/ Nov. 03 Internal Row counter 2Mx8 Bank3 Row 2Mx8 Bank 2 Pre Decoders 2Mx8 Bank 1 Column Pre Decoders Column Add Counter Burst Counter CAS Latency Data Out Control HY57V64820HGTP 2Mx8 Bank 0 Memory Cell Array Y decoders Pipe Line Control DQ0 DQ1 DQ6 DQ7 3 ...

Page 4

... V IN OUT V V DD, DDQ SOLDER (TA °C ) Symbol Min 3.0 DDQ 2 2.0 SSQ (TA ° =3.3 ± 0.3V Symbol Vtrip Voutref CL HY57V64820HGTP Rating -55 ~ 125 -1.0 ~ 4.6 -1 260 ⋅ 10 Typ. Max Unit 3.3 3 2.0 V DDQ 0 0.8 V =0V) SS Value Unit 2.4/0 1.4 ...

Page 5

... Rev. 0.1/ Nov. 03 Pin CLK A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM DQ0 ~ DQ7 Vtt=1.4V RT=250 Ω Output 50pF ± (TA ° =3.3 0.3V) DD Symbol Min 2.4 - =0V IN HY57V64820HGTP Symbol Min Max 2 6.5 I/O 50pF AC Output Load Circuit Max Unit ...

Page 6

... DD ∞ CKE ≥ V (min Input signals are stable. CL=3 ≥ (min), I =0mA All banks active CL=2 ≥ (min), All banks active RRC RRC CKE ≤ 0.2V HY57V64820HGTP Speed - -P 150 150 150 ...

Page 7

... Max Min Max Min 7 7.5 7.5 1000 1000 1000 10 7 2.5 - 2.5 - 2.5 - 2.5 - 2.5 - 2.5 5.4 - 5 5.4 - 2.7 - 2.7 - 2.7 - 1.5 - 1.5 - 1.5 - 0.8 - 0.8 - 0.8 - 1.5 - 1.5 - 1.5 - 0.8 - 0.8 - 0.8 - 1.5 - 1.5 - 1.5 - 0.8 - 0.8 - 0.8 - 1.5 - 1.5 - 1.5 - 0.8 - 0.8 - 0.8 - 1.5 - 1.5 - 1.5 5.4 5.4 5.4 HY57V64820HGTP - Max Min Max Min Max Min 1000 1000 1000 5 ...

Page 8

... HY57V64820HGTP - Min Max Min Max Min Max 120K 50 120K 50 120K ...

Page 9

... HY57V64820HGTP tRP tAC tOH 3CLKs 5.4ns 2.7ns 3CLKs 5.4ns 2.7ns 3CLKs 5.4ns 2.7ns tRP tAC tOH 3CLKs 5.4ns 2.7ns 3CLKs 5.4ns 2 ...

Page 10

... HY57V64820HGTP A10/ DQM BA ADDR code ...

Page 11

... PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package 22.327(0.8790) 22.149(0.8720) 0.150(0.0059) 0.050(0.0020) 0.400(0.016) 0.80(0.0315)BSC 0.300(0.012) Rev. 0.1/ Nov. 03 HY57V64820HGTP UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 5deg 0.210(0.0083) 0.597(0.0235) 0deg 0.120(0.0047) ...

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