MC68EN360ZP25 Motorola, MC68EN360ZP25 Datasheet
MC68EN360ZP25
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MC68EN360ZP25 Summary of contents
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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold ...
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... MC68360 USER’S MANUAL MOTOROLA ...
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... Section 8 IEEE 1149.1 Test Access Port Section 9 Applications Section 10 Electrical Characteristics Section 11 Ordering Information and Mechanical Data Appendix A Serial Performance Appendix B Development Tools and Support Appendix C RISC Microcode from RAM Appendix D MC68MH360 Product Brief MOTOROLA PREFACE MC68360 USER’S MANUAL iii ...
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... MC68360 USER’S MANUAL MOTOROLA ...
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... Interrupt Request Level (IRQ7–IRQ1)..................................................... 2-7 2.1.7 Bus Control Signals................................................................................. 2-7 2.1.7.1 Data and Size Acknowledge (DSACK1–DSACK0). ................................ 2-8 2.1.7.2 Autovector/Interrupt Acknowledge (AVEC/IACK5).................................. 2-8 2.1.7.3 Address Strobe (AS). .............................................................................. 2-8 2.1.7.4 Data Strobe (DS)..................................................................................... 2-8 MOTOROLA Thi d Title Section 1 Introduction Section 2 Signal Descriptions MC68360 USER’S MANUAL ith Table of Contents Page ...
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... Test Data Out (TDO)..............................................................................2-12 2.1.13 Initial Configuration Pins (CONFIG).......................................................2-12 2.1.14 Power Signals ........................................................................................2-13 2.1.14.1 VCCSYN and GNDSYN.........................................................................2-13 2.1.14.2 VCCCLK and GNDCLK. ........................................................................2-13 2.1.14.3 GNDS1 and GNDS2. .............................................................................2-13 2.1.14.4 VCC and GND. ......................................................................................2-13 2.1.14.5 NC4–NC1...............................................................................................2-13 2.2 System Bus Signal Index in Slave Mode ...............................................2-14 2.3 On-Chip Peripherals Signal Index..........................................................2-15 ii Title Section 3 MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Interrupt Acknowledge Cycle—Terminated Normally............................ 4-36 4.4.4.2 Autovector Interrupt Acknowledge Cycle. ............................................. 4-38 4.4.4.3 Spurious Interrupt Cycle........................................................................ 4-40 4.5 Bus Exception Control Cycles ............................................................... 4-41 4.5.1 Bus Errors ............................................................................................. 4-42 4.5.2 Retry Operation ..................................................................................... 4-44 4.5.3 Halt Operation ....................................................................................... 4-46 4.5.4 Double Bus Fault................................................................................... 4-48 MOTOROLA Title QUICC Memory Map Section 4 Bus Operation MC68360 USER’S MANUAL Table of Contents Page Number iii ...
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... Shift and Rotate Instructions..................................................................5-22 5.3.3.6 Bit Manipulation Instructions ..................................................................5-23 5.3.3.7 Binary-Coded Decimal (BCD) Instructions.............................................5-24 5.3.3.8 Program Control Instructions .................................................................5-24 5.3.3.9 System Control Instructions ...................................................................5-25 5.3.3.10 Condition Tests ......................................................................................5-26 5.3.4 Using the TBL Instructions.....................................................................5-27 5.3.4.1 Table Example 1: Standard Usage ........................................................5-28 5.3.4.2 Table Example 2: Compressed Table....................................................5-29 iv Title Section 5 CPU32+ MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Type II—Correcting Faults via RTE....................................................... 5-54 5.5.3.2.4 Type III—Correcting Faults via Software............................................... 5-54 5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart........................ 5-55 5.5.3.2.6 Type III—Correcting Faults via RTE...................................................... 5-55 5.5.3.2.7 Type IV—Correcting Faults via Software .............................................. 5-55 5.5.4 CPU32+ Stack Frames ......................................................................... 5-56 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number v ...
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... Dump Memory Block (DUMP)................................................................5-75 5.6.2.8.11 Fill Memory Block (FILL) ........................................................................5-76 5.6.2.8.12 Resume Execution (GO)........................................................................5-77 5.6.2.8.13 Call User Code (CALL) ..........................................................................5-77 5.6.2.8.14 Reset Peripherals (RST)........................................................................5-79 5.6.2.8.15 No Operation (NOP) ..............................................................................5-79 5.6.2.8.16 Future Commands .................................................................................5-80 5.6.3 Deterministic Opcode Tracking..............................................................5-80 5.6.3.1 Instruction Fetch (IFETCH) ....................................................................5-80 5.6.3.2 Instruction Pipe (IPIPE1–IPIPE0) ..........................................................5-80 5.6.3.3 Opcode Tracking during Loop Mode......................................................5-82 vi Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Double Bus Fault Monitor........................................................................ 6-9 6.3.1.2.4 Software Watchdog Timer (SWT) ........................................................... 6-9 6.3.2 Periodic Interrupt Timer (PIT)................................................................ 6-10 6.3.2.1 PIT Period Calculation........................................................................... 6-10 6.3.2.2 Using the PIT as a Real-Time Clock ..................................................... 6-11 6.3.3 Freeze Support...................................................................................... 6-11 6.3.4 Low-Power Stop Support ...................................................................... 6-11 6.4 Low Power in Normal Operation ........................................................... 6-12 MOTOROLA Title Section 6 MC68360 USER’S MANUAL Table of Contents Page Number vii ...
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... System Configuration and Protection Registers ....................................6-29 6.9.3.1 Module Configuration Register (MCR)...................................................6-29 6.9.3.2 Autovector Register (AVR).....................................................................6-34 6.9.3.3 Reset Status Register (RSR) .................................................................6-34 6.9.3.4 Software Watchdog Interrupt Vector Register (SWIV)...........................6-35 6.9.3.5 System Protection Control Register (SYPCR) .......................................6-35 6.9.3.6 Periodic Interrupt Control Register (PICR).............................................6-37 viii Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Base Register (BR) ............................................................................... 6-70 6.13.4 Option Register (OR)............................................................................. 6-74 6.13.5 DRAM-SRAM Performance Summary; ................................................. 6-78 Communication Processor Module (CPM) Introduction.............................................................................................. 7-1 7.1 RISC Controller ....................................................................................... 7-3 7.1.1 RISC Controller Configuration Register (RCCR).................................... 7-4 7.1.2 RISC Microcode Revision Number......................................................... 7-5 7.2 Command Set ........................................................................................ 7-5 7.2.1 Command Register Examples................................................................. 7-8 7.2.2 Command Execution Latency ................................................................. 7-8 MOTOROLA Title Section 7 MC68360 USER’S MANUAL Table of Contents Page Number ix ...
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... Channel Status Register (CSR) .............................................................7-32 7.6.2.8 Channel Mask Register (CMAR)............................................................7-33 7.6.2.9 Data Holding Register (DHR).................................................................7-33 7.6.3 Interface Signals ...................................................................................7-33 7.6.3.1 DREQ and DACK...................................................................................7-33 7.6.3.2 DONEx...................................................................................................7-33 7.6.4 IDMA Operation ....................................................................................7-34 7.6.4.1 Single Buffer ..........................................................................................7-34 7.6.4.2 Auto Buffer and Buffer Chaining ............................................................7-34 7.6.4.2.1 IDMA Parameter RAM ...........................................................................7-35 7.6.4.2.2 IDMA Buffer Descriptors (BDs) ..............................................................7-36 x Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... One Multiplexed Channel with Dynamic Frames .................................. 7-69 7.8.4.3 Two Multiplexed Channels with Static Frames...................................... 7-70 7.8.4.4 Two Multiplexed Channels with Dynamic Frames................................. 7-71 7.8.4.5 Programming SI RAM Entries ............................................................... 7-72 7.8.4.6 SI RAM Programming Example ............................................................ 7-75 7.8.4.7 SI RAM Dynamic Changes.................................................................... 7-75 7.8.5 SI Registers........................................................................................... 7-77 7.8.5.1 SI Global Mode Register (SIGMR) ........................................................ 7-77 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xi ...
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... Interrupts from the SCCs ....................................................................7-128 7.10.8.1 SCC Event Register (SCCE) ...............................................................7-128 7.10.8.2 SCC Mask Register (SCCM) ...............................................................7-129 7.10.8.3 SCC Status Register (SCCS) ..............................................................7-129 7.10.9 SCC Initialization.................................................................................7-129 7.10.10 SCC Interrupt Handling........................................................................7-130 7.10.11 SCC Timing Control .............................................................................7-130 7.10.11.1 Synchronous Protocols ........................................................................7-130 xii Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... S-Records Programming Example...................................................... 7-169 7.10.17 HDLC Controller .................................................................................. 7-169 7.10.17.1 HDLC Controller Key Features............................................................ 7-170 7.10.17.2 HDLC Channel Frame Transmission Processing................................ 7-171 7.10.17.3 HDLC Channel Frame Reception Processing..................................... 7-172 7.10.17.4 HDLC Memory Map............................................................................. 7-172 7.10.17.5 HDLC Programming Model ................................................................. 7-174 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xiii ...
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... BISYNC Channel Frame Reception.....................................................7-202 7.10.20.4 BISYNC Memory Map..........................................................................7-203 7.10.20.5 BISYNC Command Set........................................................................7-204 7.10.20.5.1 Transmit Commands............................................................................7-204 7.10.20.5.2 Receive Commands.............................................................................7-205 7.10.20.6 BISYNC Control Character Recognition ..............................................7-206 7.10.20.7 BSYNC-BISYNC SYNC Register.........................................................7-207 7.10.20.8 BDLE-BISYNC DLE Register...............................................................7-208 xiv Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Learning Ethernet on the QUICC ........................................................ 7-238 7.10.23.4 Connecting QUICC to Ethernet ........................................................... 7-239 7.10.23.5 Ethernet Channel Frame Transmission............................................... 7-241 7.10.23.6 Ethernet Channel Frame Reception.................................................... 7-242 7.10.23.7 CAM Interface ..................................................................................... 7-243 7.10.23.8 Ethernet Memory Map......................................................................... 7-246 7.10.23.9 Ethernet Programming Model ............................................................. 7-250 7.10.23.10 Ethernet Command Set....................................................................... 7-250 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xv ...
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... SMC UART Comparison......................................................................7-276 7.11.7.3 SMC UART Memory Map ....................................................................7-277 7.11.7.4 SMC UART Transmission Processing .................................................7-278 7.11.7.5 SMC UART Reception Processing ......................................................7-279 7.11.7.6 SMC UART Programming Model.........................................................7-279 7.11.7.7 SMC UART Command Set ..................................................................7-279 7.11.7.7.1 Transmit Commands............................................................................7-279 xvi Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... SMC as a GCI Controller..................................................................... 7-305 7.11.14.1 SMC GCI Memory Map ....................................................................... 7-306 7.11.14.1.1 SMC Monitor Channel Transmission................................................... 7-306 7.11.14.1.2 SMC Monitor Channel Reception........................................................ 7-307 7.11.14.2 SMC C/I Channel Handling ................................................................. 7-307 7.11.14.2.1 SMC C/I Channel Transmission .......................................................... 7-307 7.11.14.2.2 SMC C/I Channel Reception ............................................................... 7-307 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xvii ...
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... SPI Slave Example ..............................................................................7-330 7.12.8 SPI Interrupt Handling..........................................................................7-331 7.13 Parallel Interface Port (PIP) .................................................................7-331 7.13.1 PIP Key Features.................................................................................7-331 7.13.2 PIP Overview .......................................................................................7-332 7.13.3 General-Purpose I/O Pins (Port B) ......................................................7-333 7.13.4 Interlocked Data Transfers...................................................................7-333 7.13.5 Pulsed Data Transfers .........................................................................7-334 7.13.5.1 Busy Signal ..........................................................................................7-335 xviii Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Centronics Receiver Command Set .................................................... 7-354 7.13.8.20.1 INIT RX PARAMETERS Command .................................................... 7-354 7.13.8.20.2 CLOSE RX BD Command................................................................... 7-354 7.13.8.21 Receiver Errors ................................................................................... 7-354 7.13.8.21.1 Buffer Descriptor Busy ........................................................................ 7-354 7.13.8.22 Centronics Receive Buffer Descriptor ................................................. 7-354 7.13.8.23 Centronics Receiver Event Register (PIPE)........................................ 7-355 7.13.9 Port B Registers .................................................................................. 7-356 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xix ...
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... CPM Interrupt Configuration Register (CICR)......................................7-377 7.15.5.2 CPM Interupt Pending Register (CIPR) ...............................................7-379 7.15.5.3 CPM Interrupt Mask Register (CIMR) ..................................................7-380 7.15.5.4 CPM Interrupt In-Service Register (CISR) ...........................................7-380 7.15.6 Interrupt Handler Examples .................................................................7-381 7.15.6.1 Example 1—PC6 Interrupt Handler .....................................................7-381 7.15.6.2 Example 2—SCC1 Interrupt Handler...................................................7-381 xx Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Using the QUICC in 16-Bit Data Bus Mode........................................... 9-12 9.2 How to take A QUICC Software Test-Drive........................................... 9-13 Step 1: Decide on Reset Stack Pointer and Initial Program Counter .... 9-13 Step 2: Stay in Supervisor Mode........................................................... 9-13 Step 3: Write the VBR ........................................................................... 9-14 MOTOROLA Title Section 8 Scan Chain Test Access Port Section 9 Applications MC68360 USER’S MANUAL ...
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... Using the QUICC MC68040 Companion Mode .....................................9-31 9.4.1 MC68EC040 to QUICC Interface...........................................................9-32 9.4.1.1 MC68EC040 Reads And Writes to QUICC............................................9-32 9.4.1.2 Clocking Strategy...................................................................................9-34 9.4.1.3 Reset Strategy. ......................................................................................9-34 9.4.1.4 Interrupts................................................................................................9-34 9.4.2 Memory Interfaces .................................................................................9-37 9.4.2.1 QUICC Memory Interface Pins. .............................................................9-37 9.4.2.2 Regular EPROM. ...................................................................................9-38 9.4.2.3 Burst EPROM. .......................................................................................9-38 9.4.2.4 Flash EPROM. .......................................................................................9-41 9.4.2.5 Regular SRAM. ......................................................................................9-41 9.4.2.6 Burst SRAM. ..........................................................................................9-41 xxii Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Interfacing an MC68EC030 Master to the QUICC In Slave Mode ........ 9-74 9.8.1 MC68EC030 to QUICC Interface .......................................................... 9-74 9.8.1.1 MC68EC030 Reads and Writes to QUICC............................................ 9-75 9.8.1.2 Clocking Strategy. ................................................................................. 9-75 9.8.1.3 Reset Strategy....................................................................................... 9-77 9.8.1.4 Interrupts ............................................................................................... 9-77 9.8.1.5 Bus Arbitration....................................................................................... 9-78 9.8.1.6 Breakpoint Generation .......................................................................... 9-78 9.8.1.7 Bus Monitor Function ............................................................................ 9-78 9.8.1.8 Spurious Interrupt Monitor..................................................................... 9-78 9.8.1.9 Software Watchdog ............................................................................... 9-79 9.8.1.10 Periodic Interval Timer .......................................................................... 9-79 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xxiii ...
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... Bus Type Slave Mode Bus Arbitration AC Electrical Specifications10-49 10.16 040 Bus Type Slave Mode Internal Read/write/IACK Cycles AC Electrical Specifications10-51 10.17 040 Bus Type SRAM/DRAM Cycles Ac Electrical Specifications .......10-56 10.18 IDMA AC Electrical Specifications ......................................................10-62 10.19 PIP/PIO AC Electrical Specifications ...................................................10-64 xxiv Title Section 10 Electrical Characteristics MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Pin Assignment—357-Lead BALL Grid Array (BGA) ............................ 11-5 11.5 Package Dimensions—CQFP (FE Suffix) ............................................. 11-6 11.6 Package Dimensions—PGA (RC Suffix)............................................... 11-7 11.7 Package Dimensions—BGA (ZP Suffix) ............................................... 11-8 Development Tools and Support B.1 Motorola Software Modules.................................................................... B-1 B.2 Other protocol Software Support............................................................ B-5 B.3 Third-Party Software Support................................................................. B-6 B.4 M68360QUADS Development System ................................................... B-6 B.5 Other Development Boards.................................................................. B-10 B.6 Direct Target Development .................................................................. B-10 C ...
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... QUICC Architecture Overview ................................................................ D-2 D.2.1 CPU32+ Core.......................................................................................... D-3 D.2.2 System Integration Module (SIM60) ....................................................... D-4 D.2.3 Communications Processor Module (CPM)............................................ D-4 4.2.3.1 QUICC32 Serial Configurations .............................................................. D-5 D.2.4 The QMC Microcode............................................................................... D-7 D.2.5 Data Flow................................................................................................ D-8 D.2.6 Data Management .................................................................................. D-8 D.2.7 Performance ........................................................................................... D-9 D.2.8 Development Support ........................................................................... D-10 D.2.9 Ordering Information ............................................................................. D-10 xxvi Title Appendix D MC68MH360 Product Brief MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... QUICC Features Usable in Slave Mode • Memory Controller (Eight Banks) —Contains Complete Dynamic Random-Access Memory (DRAM) Controller —Each Bank Can Be a Chip Select or Support a DRAM Bank — Wait States MOTOROLA Thi d MC68360 USER’S MANUAL ith ...
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... Continuous Mode Transmission and Reception on All Serial Channels —2.5 Kbytes of Dual-Port RAM —14 Serial DMA (SDMA) Channels —Three Parallel I/O Registers with Open-Drain Capability —Each Serial Channel Can Have Its Own Pins (NMSI Mode) • Four Baud Rate Generators 1-2 MC68360 USER’S MANUAL MOTOROLA ...
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... Independent Transmit and Receive Routing, Frame Syncs, Clocking —Allows Dynamic Changes —Can Be internally Connected to Six Serial Channels (Four SCCs and Two SMCs) 1. SDLC is a trademark of International Business Machines. 2. AppleTalk is a registered trademark of Apple Computer, Inc. 3. DDCMP is a trademark of Digital Equipment Corporation. MOTOROLA MC68360 USER’S MANUAL Introduction 1-3 ...
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... QUICC ARCHITECTURE OVERVIEW The QUICC is 32-bit controller that is an extension of other members of the Motorola M68300 family. Like other members of the M68300 family, the QUICC incorporates the inter- module bus (IMB). (The MC68302 is an exception, having an M68000 bus on chip.) The IMB provides a common interface for all modules of the M68300 family, which allows Motorola to develop new devices more quickly by using the library of existing modules ...
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... Regardless of the choice of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32- bit system bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system bus mode. MOTOROLA MC68360 USER’S MANUAL Introduction 1-5 ...
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... Although the features of the SIM60 do not exactly correspond to those of the MC68302 SIM, they are very similar. The QUICC SIM60 combines the best MC68302 SIM features with the best MC68340 SIM features for improved performance. 1-6 MC68360 USER’S MANUAL MOTOROLA ...
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... Although the registers used to initialize the QUICC CPM are new (for example, the SCM on the MC68302 is replaced with the GSMR and PSMR on the QUICC), most registers retain their original purpose such as the SCC event, SCC mask, SCC status, and com- MOTOROLA MC68360 USER’S MANUAL Introduction ...
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... From a logic standpoint, however, a glueless system is maintained. 1-8 CS0 OE WE0 DATA ADDRESS RAS1 R/W MC68360 USER’S MANUAL 8-BIT BOOT EPROM (FLASH OR REGULAR) CE (ENABLE) OE (OUTPUT ENABLE) WE (WRITE) DATA ADDRESS 16- OR 32-BIT DRAM SIMM (OPTIONAL PARITY) RAS CAS3–CAS0 W (WRITE) DATA ADDRESS PARITY MOTOROLA ...
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... Figure 1-4 shows the Ethernet LAN capability of the QUICC. An external SIA transceiver is required to complete the interface to the media. This functionality is implemented in the MC68160 enhanced Ethernet serial transceiver (EEST MOTOROLA CS0 OE WE0 CS7 ...
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... EEST QUICC MC68160 SCC1 EEST QUICC MC68160 SCC1 EEST QUICC RS422 SCC XCVR QUICC RS422 SCC XCVR MC68302 MC68195 LA RS422 SCC XCVR NOTE: The QUICC implements the AppleTalk LAN protocol without the need for the MC68195. MC68360 USER’S MANUAL MOTOROLA ...
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... Figure 1-7 shows the original SDLC application, which can be implemented by both QUICCs and MC68302s. Figure 1-7. FSDLC Bus Implementation Figure 1-8 shows a UART LAN configuration that is supported by both the QUICC and the MC68302, as well as many other industry UARTs. MOTOROLA QUICC SCC QUICC HDLC BUS ...
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... Figure 1-8. UART LAN Implementation Figure 1-9 shows how the SPIs on the QUICC can be used to connect devices together into a local bus. The SPI exists on many other Motorola devices, such as the MC68HC11 micro- controller, and a number of peripherals such as A/D and D/A converters, LED drivers, LCD drivers, real-time clocks, serial EEPROM, PLL frequency synthesizers, and shift registers. ...
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... Figure 1-12 shows how the parallel interface port (PIP) can be used to implement the Cen- tronics interface connection. The QUICC may be the peripheral or the host. QUICC NOTE: The QUICC can communicate over a Centronics Interface. Figure 1-12. Centronics Interface Implementation MOTOROLA SPI BUS SCP MASTER SPI BUS ...
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... Figure 1-16 shows other point-to-point options that are possible with the QUICC and the MC68302. 1-14 PARALLEL INTERFACE PIP PIP 8 DATA LINES HDLC/SDLC BISYNC UART TRANSPARENT SCC SCC HDLC/SDLC BISYNC UART TRANSPARENT SYNCHRONOUS UART SS#7 SCC SCC MC68360 USER’S MANUAL QUICC MC68302 QUICC MOTOROLA ...
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... Figure 1-18 shows that the QUICC time-slot assigner can support two TDM buses. Each TDM bus can different format—for example, one TDM can line, and one can be a CEPT line. Also this technique could be used to bridge frames from basic rate ISDN to a T1/CEPT line, etc. MOTOROLA SMC UART TRANSPARENT ...
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... AND SMCs MAY BE CONNECTED TO ANY TDM. with the time slot assigner. QUICC SCC SCC TIME SCC SLOT SCC ASSIGNER SMC SMC QUICC SCC SCC TIME SCC SLOT SCC ASSIGNER SMC SMC MC68360 USER’S MANUAL TDM BUS 1 TDM BUS 2 TDM BUS MOTOROLA ...
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... SMCs, two SPIs, four IDMAs, etc. Each QUICC uses its own DMA capability, but the CPU32+ is the only processor in the system. More QUICCs can be easily supported on the system bus, if desired. Figure 1-21. Master-Slave QUICC Implementation MOTOROLA QUICC MOTOROLA SCC1 TRANSCEIVER SCC2 SPI TIME ...
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... When slave mode, the QUICC can also be interfaced to any MC68030-type bus master instead of the MC68EC040. MC68EC040 Figure 1-22. MC68040 Companion Mode 1-18 MC68EC040 SUPPORT FUNCTIONS SYSTEM BUS CONTROL MEMORY CONTROLLER EPROM DRAM ADDRESS MUXs SRAM MC68360 USER’S MANUAL QUICC SLAVE CPU32+ SCC SCC SCC SCC SMC SMC SPI MOTOROLA ...
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... WE1—Corresponds to A30 and selects data bits 23–16. Also may be referred to as UM- WE. WE2—Corresponds to A29 and selects data bits 15–8. Also may be referred to as LMWE. WE3—Corresponds to A28 and selects data bits 7–0. Also may be referred to as LLWE. MOTOROLA Thi d MC68360 USER’S MANUAL t ...
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... RESETH RESETS HALT BERR/TEA PERR INTERRUPT CONTROL IRQ1/IOUT0/RQOUT IRQ4/IOUT1 IRQ6/IOUT2 IRQ2,3,5,7 AVEC/IACK5/AVECO MEMORY CONTROLLER CS6–CS0/RAS6–RAS0 CS/RAS7/IACK7 CAS3–CAS0/IACK6,3,2,1 TEST TRIS/TS BKPT/BKPTO/DSCLK FREEZE/CONFIG2/MBARE IPIPE1/RAS1DD/BCLRI IPIPE0/BADD2/DSO IFETCH/BADD3/DSI TCK TMS TDI TDO TRST CLOCK XTAL EXTAL XFC MODCK1–MODCK0 CLKO2–CLKO1 MOTOROLA ...
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... Output Enable/ Address Multiplex Interrupt Interrupt Request Control Level 7–1 Autovector/Interrupt Acknowledge 5 MOTOROLA Mnemonic A27–A0 Lower 27 bits of address bus. (I/O) A31–A28/ Upper four bits of address bus (I/O), or byte write enable sig- WE0–WE3 nals (O) for accesses to external memory or peripherals. Identifies the processor state and the address space of the FC3– ...
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... Special ground for fast AC timing on certain system bus sig- GNDS1 nals. Special ground for fast AC timing on certain system bus sig- GNDS2 nals. VCC, GND Power supply and return to the QUICC. NC4–NC1 Four no-connect pins. MC68360 USER’S MANUAL Function MOTOROLA ...
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... Address Space Reserved (Motorola User Data Space User Program Space Reserved (User Reserved (Motorola Supervisor Data Space Supervisor Program Space Supervisor CPU Space DMA Space NOTE MC68360 USER’S MANUAL Signal Descriptions ...
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... RAS2DD pin to increase the RAS2 line drive capability. 2.1.5.2 CHIP SELECT/ROW ADDRESS SELECT/INTERRUPT ACKNOWLEDGE (CS7/ RAS7/IACK7). This pin can be programmed as a CS7/RAS7 pin or as the IACK7 line. See Section 6 System Integration Module (SIM60) for more information on this selection. 2-6 NOTE MC68360 USER’S MANUAL chip- MOTOROLA ...
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... IRQ6–IRQ1 are internally maskable interrupts. Refer to Section 5 CPU32+ for more infor- mation on the interrupt request lines. 2.1.7 Bus Control Signals These signals control the bus transfer operations of the QUICC. Refer to Section 4 Bus Operation for more information on these signals. MOTOROLA – ) IRQ7 IRQ1 MC68360 USER’ ...
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... Complete cycle—data bus port size is 8 bits. 1 (Negated) Complete cycle—data bus port size is 16 bits. 0 (Asserted) Complete cycle—data bus port size is 32 bits. Table 2-4. SIZx Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word Bytes 0 0 Long Word MC68360 USER’S MANUAL Result MOTOROLA ...
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... BUS CLEAR OUT/INITIAL CONFIGURATION/ROW ADDRESS SELECT DOUBLE-DRIVE (BCLRO/CONFIG1/RAS2DD). This pin can be programmed as the bus clear out output or as the initial configuration pin 1 input signal during system reset or as the RAS2DD output double-drive signal. MOTOROLA NOTE MC68360 USER’S MANUAL Signal Descriptions ...
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... These signals are used by the QUICC for controlling or generating the system clocks. Refer to Section 6 System Integration Module (SIM60) for more information on these clock signals. 2.1.10.1 SYSTEM CLOCK OUTPUTS (CLKO2–CLKO1). These output signals reflect the general system clock and are used as the bus timing reference by external devices. CLKO1 2-10 MC68360 USER’S MANUAL MOTOROLA ...
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... RAS1DD). This active-low output signal is used to track movement of words through the instruction pipeline. This signal also functions as a second output of the RAS1 signal to increase fanout capability. 2.1.11.4 BREAKPOINT/DEVELOPMENT SERIAL CLOCK (BKPT/DSCLK). This low input signal is used to signal a hardware breakpoint to the CPU32+. Additionally, this MOTOROLA Multi. Factor EXTAL Freq. ( (examples) ...
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... After reset, these pins may be programmed to their other function. The CONFIG2–CONFIG0 lines have internal pullup resistors so that if they are left floating, the default selection will be 111. See Section 6 System Integration Module (SIM60) for more information. 2-12 MC68360 USER’S MANUAL MOTOROLA ...
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... VCC AND GND. These pins are the rest of the power and ground connections for the QUICC. 2.1.14.5 NC4–NC1. These four pins should not be connected on the QUICC package. They are reserved for future enhancements. MOTOROLA Table 2-6. Initial Configuration 0 Slave mode; global CS 8-bit size; MBAR at $003FF00. ...
Page 62
... Provides an MBAR access enable (I), or the initial QUICC con- CONFIG2 figuration select. (I) IRQ6,4,1/ Provides an interrupt request to the QUICC interrupt controller IOUT2–IOUT0/ (I), or interrupt output signals (O) (either RQOUT as a single re- IRQOUT quest or IOUT2–IOUT0 encoded). MC68360 USER’S MANUAL Slave Mode Function MOTOROLA ...
Page 63
... TIMER Timer Gate TGATE2–TGATE1 An input to a timer that enables/disables the counting function. (I) Timer Input TIN4–TIN1 MOTOROLA Slave Mode Mnemonic PRTY0/IOUT2 Parity signals for D31–D24 writes/reads from/to external mem- ory bank (I/O), or interrupt output 2 signal (O). PRTY1/IOUT1 Parity signals for D23–D16 writes/reads from/to external mem- ory bank (I/O) or interrupt output 1 signal. (O) Parity signals for D15– ...
Page 64
... PIP Data I/O Pins This input causes the PIP output data to be placed on the PIP data STRBO pins. This input causes data on the PIP data pins to be latched by the PIP STRBI as input data. Ethernet receive frame. MC68360 USER’S MANUAL Function MOTOROLA ...
Page 65
... Signal Descriptions 2-17 MC68360 USER’S MANUAL MOTOROLA ...
Page 66
... Signal Descriptions 2-18 MC68360 USER’S MANUAL MOTOROLA ...
Page 67
... The 8-Kbyte block is divided into two 4-Kbyte sections. The RAM occupies the first section; the internal registers occupy the second section. The location of the QUICC registers is shown in Figure 3-1. MOTOROLA Thi d MC68360 USER’S MANUAL t ...
Page 68
... It may be partitioned in several ways, allowing programmable partition sizes to fit the system requirements. This is described in Section 7 Communication Processor Mod- ule (CPM). 3-2 DPRBASE (DUAL-PORT RAM BASE) DUAL-PORT RAM REGB (REGISTER BASE) = DPRBASE + 4K INTERNAL REGISTERS Figure 3-1. QUICC Memory Map NOTE MC68360 USER’S MANUAL MBAR (SIM) MOTOROLA ...
Page 69
... See the particular sub-module description within Section 7 Communication Processor Module (CPM) for further information. Table 3-2. CPM Sub-Module Base Addresses Parameter RAM Page MOTOROLA Table 3-1. Dual-Port RAM Map Size Block 1024 Bytes Dual-Port RAM 512 Bytes Dual-Port RAM 256 Bytes Dual-Port RAM 256 Bytes Dual-Port RAM ...
Page 70
... Bold letters mark registers that are restricted to supervisor ac- cess. 3.3.1 SIM Registers Memory Map Table 3-3 lists the SIM registers memory map. 3-4 SMC1 Base DPRBASE + $E80 SCC4 Base DPRBASE + $F00 IDMA2 Base DPRBASE + $F70 SMC2 Base DPRBASE + $F80 NOTES MC68360 USER’S MANUAL MOTOROLA ...
Page 71
... REGB + 0060 BR1 32 REGB + 0064 OR1 32 REGB + 0068 to REGB +006f REGB + 0070 BR2 32 REGB + 0074 OR2 32 MOTOROLA Description Module Configuration Register Reserved 8 Autovector Register 8 Reset Status Register Reserved 8 CLKO Control Register Reserved PLL Control Register Reserved Clock Divider Control Register Port E Pin Assignment Register ...
Page 72
... IDMA1 Function Code Register MC68360 USER’S MANUAL 0000 0050 H F000 000x H 0000 0050 H F000 000x H 0000 0050 H F000 000x H 0000 0050 H F000 000x H 0000 0050 H F000 000x H Reset Value Block 0000 H IDMA1 0000 0000 0000 0000 0000 0000 0000 00 MOTOROLA ...
Page 73
... PCPAR 16 REGB + 564 PCSO 16 REGB + 566 PCDAT 16 REGB + 568 PCINT 16 REGB + 56a to REGB + 57f REGB + 580 TGCR 16 MOTOROLA 8 Reserved 8 Channel Mask Register 8 Reserved 8 IDMA1 Channel Status Register Reserved 8 SDMA Status Register 8 Reserved SDMA Configuration Register SDMA Address Register Reserved IDMA2 Mode Register ...
Page 74
... MC68360 USER’S MANUAL 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 0000 0000 0000 0000 CP 0000 H 0000 0000 xx00 0000 H BRG xx00 0000 H xx00 0000 H xx00 0000 H 0000 0000 SCC1 0000 0000 0000 MOTOROLA ...
Page 75
... REGB + 681 REGB + 682 SMCMR1 16 REGB + 686 SMCE1 REGB + 68a SMCM1 REGB + 68C MOTOROLA SCC1 Data Sync. Register SCC1 Event Register SCC1 Mask Register 8 SCC1 Status Register Reserved SCC2 General Mode Register SCC2 General Mode Register SCC2 Protocol-Specific Mode Register 0000 SCC2 Transmit on Demand SCC2 Data Sync ...
Page 76
... SI Status Register 8 SI Command Register Reserved SI Clock Route SI RAM Pointers Reserved MC68360 USER’S MANUAL 0000 SMC2 00 00 0000 H SPI 0000 H PIP 0000 xxx0 0000 H xxx0 0000 H 0000 H xxxX XXXX 0000 0000 0000 0000 H 0000 0000 XXXX MOTOROLA ...
Page 77
... The user should be aware that misalignment of word or long- word operands can cause the CPU32+ to perform multiple bus cycles for operand transfers; therefore, processor performance is optimized if word and long-word memory operands are MOTOROLA Thi d NOTE MC68360 USER’S MANUAL ...
Page 78
... In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this sec- tion. CLK EXT Figure 4-1. Input Sample Window 4 SAMPLE WINDOW MC68360 USER’S MANUAL su MOTOROLA ...
Page 79
... Address Spaces Reserved (Motorola User Data Space User Program Space Reserved (User Reserved (Motorola Supervisor Data Space Supervisor Program Space Supervisor CPU Space DMA space MC68360 USER’S MANUAL Bus Operation 4-3 ...
Page 80
... The lower middle write enable (WE2) indicates that the lower middle eight bits of the data bus (D15–D8) contain valid data during a write cycle. The lower write enable (WE3) indicates that the lower eight bits of the data bus contain valid data during a write cycle. 4-4 MC68360 USER’S MANUAL MOTOROLA ...
Page 81
... BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can be used in the absence of DSACKx to indicate a bus error condition. BERR can also be asserted in conjunction with DSACKx to indicate a bus error condition, provided it meets the MOTOROLA NOTE MC68360 USER’S MANUAL Bus Operation ...
Page 82
... The addressed device uses the DSACKx signals to indicate 4-6 Table 4-2. DSACKx Encoding DSACK0 Result 1 Insert Wait States in Current Bus Cycle 0 Complete Cycle—Data Bus Port Size is 8 Bits 1 Complete Cycle—Data Bus Port Size is 16 Bits 0 Complete Cycle—Data Bus Port Size is 32 Bits MC68360 USER’S MANUAL MOTOROLA ...
Page 83
... For example, OP0 can be routed to D24–D31, as would be the normal case can be routed to any other byte position to support a misaligned transfer. The same is true for any of the operand bytes. The positioning of bytes is determined by the size and address outputs. MOTOROLA 0P0 0P1 0P2 ...
Page 84
... D23–D16 D15–D8 BYTE 1 BYTE 2 BYTE 1 16-BIT PORT BYTE 3 8-BIT PORT Table 4-3. SIZx Encoding SIZ1 SIZ0 Size 0 1 Byte 1 0 Word Bytes 0 0 Long Word MC68360 USER’S MANUAL 0P3 3 INTERNAL TO THE MC68360 D7–D0 EXTERNAL BUS BYTE 3 32-BIT PORT MOTOROLA ...
Page 85
... SIZ0, SIZ1, A0 0000. The port latches the data on bits D16–D31 of the data bus, asserts DSACK1 (DSACK0 remains negated), and the QUICC terminates the bus cycle. It then starts a new bus cycle with SIZ0, SIZ1, A0 1010 to transfer the remaining MOTOROLA A1 A0 ...
Page 86
... OP3 x OP3 OP3 x x OP2 OP3 x OP3 OP2 OP3 OP2 x OP2 OP2 OP3 x OP1 OP2 OP3 OP2 OP1 OP2 x OP2 OP1 OP1 OP2 OP3 OP0 OP1 OP2 OP1 OP0 OP1 OP0 x OP0 0 0P3 MEMORY CONTROL A0 DSACK1 DSACK0 MOTOROLA ...
Page 87
... Although the QUICC does not enforce any alignment restrictions for data operands (including PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands MOTOROLA ...
Page 88
... Attempting to prefetch an instruction word at an odd address causes an address error exception. 15 WORD OPERAND 0P2 D31 DATA BUS BYTE MEMORY 0P2 0P3 Figure 4-6. Example of Word Transfer to Byte Port 4-12 0 0P3 D24 MC68360 SIZ1 SIZ0 MC68360 USER’S MANUAL MEMORY CONTROL A0 DSACK1 DSACK0 MOTOROLA ...
Page 89
... SIZx signals indicating one byte remaining to be transferred. The address offset (A2–A0) is now 100; the port latches the final byte, and the operation is complete. Figure 4-9 shows the associated bus transfer signal timing. MOTOROLA S0 S2 ...
Page 90
... OP3 Figure 4-8. Misaligned Long-Word Transfer to Word Port Example 4-14 LONG-WORD OPERAND 0P1 0P2 D16 MC68360 LSB SIZ1 SIZ0 A2 A1 0P0 0P2 XXX MC68360 USER’S MANUAL 0 0P3 MEMORY CONTROL DSACK1 DSACK0 MOTOROLA ...
Page 91
... Figure 4-9. Misaligned Long-Word Transfer to Word Port Timing Figure 4-10 and Figure 4-11 show a word transfer to an odd address in word-organized memory. This example is similar to the one shown in Figure 4-8 and Figure 4-9 except that the operand is word sized and the transfer requires only two bus cycles. MOTOROLA ...
Page 92
... WORD OPERAND 15 OP2 D31 DATA BUS WORD MEMORY MSB XXX 0P3 Figure 4-10. Misaligned Word Transfer to Word Port Example 4-16 0 OP3 D16 MC68360 LSB SIZ1 SIZ0 0P2 XXX MC68360 USER’S MANUAL MEMORY CONTROL DSACK1 DSACK0 MOTOROLA ...
Page 93
... Only one byte can be trans- ferred in the first bus cycle. The second bus cycle then consists of a three-byte access to a long-word boundary. Since the memory is long-word organized, no further bus cycles are necessary. MOTOROLA ...
Page 94
... LONG-WORD MEMORY MSB UMB XXX XXX 0P1 0P2 Figure 4-12. Misaligned Long-Word Transfer to Long-Word Port Example 4-18 0 0P2 0P3 D0 LMB LSB SIZ1 SIZ0 0P0 0P0 0 0P3 XXX 1 MC68360 USER’S MANUAL MC68EC030 MEMORY CONTROL DSACK1 DSACK0 MOTOROLA ...
Page 95
... The combination of operand size, operand alignment, and port size determines the number of bus cycles required to perform a particular memory access. Table 4-7 lists the number of bus cycles required for different operand sizes to different port sizes with all possible align- ment conditions for write cycles and read cycles. MOTOROLA ...
Page 96
... DSACKx, the QUICC inserts wait cycles in clock-period incre- ments until DSACKx is recognized. BERR and/or HALT can be asserted after DSACKx is asserted. BERR and/or HALT must be asserted within the time specified after DSACKx is 4-20 on Write Bus Cycles Number of Bus Cycles 1:2:4 N/A N/A 1:1:1 1:1:1 1:1:1 1:1:2 1:2:2 1:1:2 1:2:4 2:3:4 2:2:4 MC68360 USER’S MANUAL 11 N/A 1:1:1 2:2:2 2:3:4 MOTOROLA ...
Page 97
... S4. Figure 4-14 shows the DSACKx timing for a read with two wait states, followed by a fast termination read and write. MOTOROLA MC68360 USER’S MANUAL Bus Operation ...
Page 98
... Bus operations are described in terms of external bus states. 4- TWO WAIT STATES IN READ FAST TERMINATION READ NOTES MC68360 USER’S MANUAL FAST TERMINATION WRITE MOTOROLA ...
Page 99
... DRIVE SIZE (SIZ1–SIZ0) (ONE BYTE) 5) ASSERT AS, DS, AND OE TERMINATE OUTPUT TRANSFER 1) LATCH DATA 2) NEGATE AS, DS, AND OE START NEXT CYCLE Figure 4-16. Byte Read Cycle Flowchart MOTOROLA PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31–D0 3) DRIVE DSACKx SIGNALS TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 ...
Page 100
... WORD SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 WORD READ Figure 4-17. Byte and Word Read Cycles—32-Bit Port Timing 4- BYTE 0P2 0P3 0P3 BYTE READ MC68360 USER’S MANUAL 0P3 BYTE READ MOTOROLA ...
Page 101
... State 0—The read cycle starts in state 0 (S0). During S0, the QUICC places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the cycle. The QUICC drives R/W high for a read cycle. SIZ1 and SIZ0 become valid, indicating the number of bytes requested for transfer. MOTOROLA ...
Page 102
... NEGATE AS AND DS AND WEx 2) REMOVE DATA FROM D31–D0 START NEXT CYCLE Figure 4-19. Write Cycle Flowchart 4-26 EXTERNAL DEVICE PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31–D0 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) TERMINATE CYCLE 1) NEGATE DSACKx MC68360 USER’S MANUAL MOTOROLA ...
Page 103
... During this state, any or all of the byte write enables (WE0, WE1, WE2, and WE3) are asserted simultaneously with AS. State 2—During S2, the QUICC places the data to be written onto D31–D0 and samples DSACKx at the end of S2. MOTOROLA ...
Page 104
... QUICC asserts RMC to indicate that an indivisible operation is occurring. The QUICC does not issue a bus grant (BG) signal in response to a bus request (BR) signal during this operation. Figure 4- example of a functional timing diagram of a read-modify-write instruction specified in terms of clock periods. 4-28 MC68360 USER’S MANUAL MOTOROLA ...
Page 105
... If DSACKx is not recognized by the start of S3, the QUICC inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchro- MOTOROLA S2 S4 ...
Page 106
... S5. If more than one write cycle is required, S0–S5 are repeated for each write cycle. The external device keeps DSACKx asserted until it detects the negation (whichever it detects first). The device must remove its data and 4-30 MC68360 USER’S MANUAL MOTOROLA ...
Page 107
... CPU space. The CPU space type, which is encoded on A19–A16 during a CPU space operation, indicates the function that the QUICC is performing. On the QUICC, four of the encodings are implemented as shown in Figure 4- 22. All unused values are reserved by Motorola for additional CPU space types. FUNCTION CODE ...
Page 108
... BKAR and BKCR discussion in Section 6 System Integration Module (SIM60) for details). The breakpoint operation flowchart is shown in Figure 4-23. Figure 4-24 and Figure 4-25 show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes supplied on the cycle and with an exception signaled, respectively. 4-32 NOTE MC68360 USER’S MANUAL MOTOROLA ...
Page 109
... CONTINUE PROCESSING IF BREAKPOINT INSTRUCTION EXECUTED: 1) INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED: 1) INITIATE HARDWARE BREAKPOINT PROCESSING Figure 4-23. Breakpoint Operation Flowchart MOTOROLA IF BREAKPOINT INSTRUCTION EXECUTED: 1) PLACE REPLACEMENT OPCODE ON DATA BUS 2) ASSERT DSACKx 1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKPT PIN ASSERTED: 1) ASSERT DSACKx ...
Page 110
... BERR HALT BKPT BREAKPOINT OCCURS Figure 4-24. Breakpoint Acknowledge Cycle Timing (Opcode Returned) 4- BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ INSTRUCTION WORD FETCH MC68360 USER’S MANUAL CPU SPACE FETCHED INSTRUCTION EXECUTION BREAKPOINT ACKNOWLEDGE MOTOROLA ...
Page 111
... BREAKPOINT OCCURS Figure 4-25. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 4.4.2 LPSTOP Broadcast Cycle The LPSTOP broadcast cycle is generated by the CPU32+ executing the LPSTOP instruc- tion. The external bus interface must get a copy of the interrupt mask level from the CPU32+, MOTOROLA ...
Page 112
... The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in 4.4.4.2 Autovector Interrupt Acknowledge Cycle. 4- — MC68360 USER’S MANUAL MOTOROLA 0 I0 ...
Page 113
... PORT SIZE) 2) ASSERT DSACKx (OR AVEC IF NO VECTOR NUMBER) RELEASE 1) NEGATE DSACKx Figure 4-26. Interrupt Acknowledge Cycle Flowchart MOTOROLA 1) SYNCHRONIZE IRQ7–IRQ1 2) COMPARE IRQ7–IRQ1 TO MASK LEVEL AND WAIT FOR INSTRUCTION TO COMPLETE 3) ASSERT BCLRO 4) PLACE INTERRUPT LEVEL ON A1–A3; TYPE FIELD (A19–A16 SET R/W TO READ 6) SET FC3– ...
Page 114
... AVEC to terminate the cycle. The DSACKx signals may not be asserted 4- 0–2 CLOCKS INTERRUPT LEVEL CPU SPACE 1 BYTE VECTOR FROM 16-BIT PORT VECTOR FROM 8-BIT PORT INTERNAL ARBITRATION IACK CYCLE MC68360 USER’S MANUAL WRITE STACK MOTOROLA ...
Page 115
... AVEC pin will not be asserted externally). Seven distinct autovectors can be used, corresponding to the seven levels of interrupt available with signals IRQ7–IRQ1. Figure 4-28 shows the timing for an autovector operation. MOTOROLA MC68360 USER’S MANUAL Bus Operation ...
Page 116
... When no internal module (including the SIM60, which responds for external requests) responds during an interrupt acknowledge cycle by arbitrating for the 4- 0–2 CLOCKS* INTERRUPT LEVEL CPU SPACE 1 BYTE INTERNAL ARBITRATION IACK CYCLE MC68360 USER’S MANUAL WRITE STACK MOTOROLA ...
Page 117
... To ensure predictable operation, BERR and HALT should be negated according to the specifications in Section 10 Electrical Characteristics. DSACKx, BERR, and HALT may be negated after AS. If DSACKx or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. MOTOROLA MC68360 USER’S MANUAL Bus Operation 4-41 ...
Page 118
... Normal cycle terminate and halt; continue when HALT negated Terminate and take bus error exception, possibly deferred Terminate and take bus error exception, possibly deferred Terminate and retry when HALT negated Terminate and retry when HALT negated. A MC68360 USER’S MANUAL Result MOTOROLA ...
Page 119
... Exceptions are taken in both cases. (Refer to Section 5 CPU32+ for details of bus error exception processing CLKO1 A31–A0 FC3–FC0 R DSACKx D31–D0 BERR READ CYCLE WITH BUS Figure 4-29. Bus Error without DSACKx MOTOROLA INTERNAL ERROR PROCESSING MC68360 USER’S MANUAL Bus Operation STACK WRITE 4-43 ...
Page 120
... After a synchronization delay, the QUICC retries the previous cycle using the same access information (address, function code, size, etc.). BERR should be negated before S2 of the retried cycle to ensure correct operation of the retried cycle. 4- WRITE INTERNAL CYCLE PROCESSING MC68360 USER’S MANUAL S2 S4 STACK WRITE MOTOROLA ...
Page 121
... When the relinquish and retry is asserted during an internal mas- ter's word access to an 8-bit port, and the external master that takes the bus performs an external-to-internal bus cycle, the en- MOTOROLA ...
Page 122
... The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, sin- gle instructions, or changes in program flow. 4- WRITE HALT CYCLE MC68360 USER’S MANUAL S2 S4 WRITE RERUN MOTOROLA ...
Page 123
... This is due to a pipelining characteristic of the QUICC coupled with the HALT signal being asserted late into an internal-to-external bus cycle. Note that show cycles mode is not the normal configura- tion for the QUICC. MOTOROLA NOTES MC68360 USER’S MANUAL Bus Operation 4-47 ...
Page 124
... QUICC. However, bus arbitration can still occur (refer to 4.6 Bus Arbitration). A second bus error or address error that occurs after exception processing has 4- READ HALT (ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) Figure 4-33. HALT Timing MC68360 USER’S MANUAL READ MOTOROLA ...
Page 125
... BGACK and maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: it must have MOTOROLA NOTE MC68360 USER’S MANUAL ...
Page 126
... NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3) NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP 1) NEGATE BGACK MC68360 USER’S MANUAL MOTOROLA ...
Page 127
... CLKO1 A31–A0 D31– DSACK1–DSACK0 BR BG BGACK NOTE: BR has synchronous timing. BR has asynchronous timing. Figure 4-35. Bus Arbitration Timing Diagram—Idle Bus Case MOTOROLA MC68360 USER’S MANUAL Bus Operation 4-51 ...
Page 128
... BGACK is received while the BR is active, the QUICC remains bus master once BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise external device determines that it no longer requires use of the bus before it has been granted mastership. 4- MC68360 USER’S MANUAL MOTOROLA ...
Page 129
... When working in asynchronous mode (ASTM bit in the MCR is cleared) and SHEN0– and one of the QUICC internal masters requests an external accesses, the mini- mum time depends on internal synchronization plus one clock. • If SHEN1–SHEN0 = 1 , another clock is added for internal bus arbitration. MOTOROLA MC68360 USER’S MANUAL Bus Operation 4-53 ...
Page 130
... The QUICC does not allow arbitration of the external bus during the RMC sequence. For the duration of this sequence, the QUICC ignores the BR input. If mastership of the bus is required during an RMC operation, BERR must be used to abort the RMC sequence. 4-54 MC68360 USER’S MANUAL MOTOROLA ...
Page 131
... Bus Arbitration. When acting as one or more of the QUICC internal masters (refresh cycles, IDMA, and SDMA), the QUICC will output the BR signal. Systems that in- clude several devices that can become bus master require external circuitry to assign prior- ities to the devices, so that when two or more external devices attempt to become bus MOTOROLA + RA B ...
Page 132
... EXTERNAL MASTER ACCESS TO DUAL PORT RAM QUICC REQUIRES EXTERNAL BUS HALT IS ASSERTED AND DRAM REFRESH DOES NOT REQUIRE EXTERNAL BUS QUICC OWNS BUS BR NEGATED BGACK ASSERTED QUICC STILL NEEDS BUS MC68360 USER’S MANUAL QUICC WAITING FOR BUS BR ASSERTED MOTOROLA ...
Page 133
... QUICC internal master requests the bus only asserted by QUICC during the state "QUICC Owns Bus", otherwise BB is three-stated by the QUICC. Figure 4-39. MC68040 Companion Mode Bus Arbitration State Machine MOTOROLA 040 STILL NEEDS BUS 040 OWNS ...
Page 134
... See Figure 4-40 for the slave mode bus arbitration timing diagram. CLKO1 A31–A0 D31– R/W DSACK1-DSACK0 BR (OUT) BG (IN) BGACK (IN/OUT) NOTES: 1. Synchronous arbitration with SHEN1–SHEN0 = 00. 2. Minimum bus idle time. Figure 4-40. Slave Mode Bus Arbitration Timing Diagram 4- MC68360 USER’S MANUAL S5 MOTOROLA ...
Page 135
... QUICC (see 4.3 Data Transfer Cycles). The QUICC supports the interrupt acknowledge cycles presented in 4.4.4 Interrupt Acknowledge Bus Cycles. The QUICC also supports the MC68EC040 read and write accesses and inter- rupt acknowledge cycles (see Figure 4-41–Figure 4-44). MOTOROLA NOTE NOTE NOTE MC68360 USER’ ...
Page 136
... TM2–TM0 R TBI D31–D0 Figure 4-41. MC68EC040 Internal Registers Read Cycle CLKO1 A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TT0 R TBI D31–D0 Figure 4-42. MC68EC040 Internal Registers Write Cycle 4- MC68360 USER’S MANUAL CW CW MOTOROLA ...
Page 137
... C1 C2 CLKO1 A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TM0 R TBI D31–D8 D7–D0 IACK7 IACK1 Figure 4-44. MC68EC040 Interrupt Acknowledge Cycle MOTOROLA INTERRUPT LEVEL INTERNAL ARBITRATION INTERRUPT LEVEL INTERNAL ARBITRATI0N MC68360 USER’S MANUAL Bus Operation CW CW ...
Page 138
... The external data bus drivers are enabled so that data becomes valid on the external bus as soon available on the internal bus. State 0 – The address, function codes, read/write, and size pins change to begin the next cycle. Data from the preceding cycle is valid through state 0. 4-62 MC68360 USER’S MANUAL MOTOROLA ...
Page 139
... Asynchronous reset sources indicate a catastrophic failure, and the reset controller logic immediately resets the system. Resetting the QUICC causes any bus cycle in progress to terminate as if DSACKx or BERR had been asserted. In addition, the QUICC appropriately initializes registers for a reset exception. MOTOROLA S0 S0 S41 S42 ...
Page 140
... Asynchronous INTRST Clock Asynchronous INTRST CPU32+ Asynchronous INTRST 512 CYCLES T 32 CLKS NOTE MC68360 USER’S MANUAL INTSYSRST CLKRST EXTSYSRST — — EXTRST INTSYSRST CLKRST EXTSYSRST INTSYSRST — EXTSYSRST INTSYSRST CLKRST EXTSYSRST INTSYSRST CLKRST EXTSYSRST 2 — — EXTRST T 14 CLKS MOTOROLA ...
Page 141
... The bus arbitration circuitry is only reset during a power-on reset. It may be used during all other resets. In QUICC slave mode (disable CPU32+) the reset operates the same as in the normal (mas- ter) mode except that the RESET instruction does not exist. MOTOROLA 512 14 CLOCKS CLKOUT ...
Page 142
... In the case where the CP32+ excutes a RESET command, the QUICC drives RESETS pin. In that case RESETS will be driven from CLOCK low (not CLOCK high as in all other cases). This requires a special AC timing parameter which is spec 58A in 10.9 Bus Operation AC Timing Specifications. 4-66 NOTE MC68360 USER’S MANUAL MOTOROLA ...
Page 143
... Although the CPU32+ does not enforce any align- ment restrictions for data operands (including PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands that are misaligned. For maximum performance, data items should be MOTOROLA Thi d MC68360 USER’S MANUAL t ...
Page 144
... Additional Addressing Modes —Scaled Index —Address Register Indirect with Base Displacement and Index —Expanded PC Relative Modes —32-Bit Branch Displacements • Instruction Set Additions —High-Precision Multiply and Divide —Trap on Condition Codes —Upper and Lower Bounds Checking 5-2 MC68360 USER’S MANUAL MOTOROLA ...
Page 145
... Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination condition and count are checked after each execution of the data operations of the looped instruction. The CPU32+ automatically exits the loop mode during interrupts or other exceptions. MOTOROLA INSTRUCTION UNIT PREFETCH ...
Page 146
... To support generic handlers, the processor places the vector offset in the exception stack frame. The processor also marks the frame with a frame format. The format 5-4 ONE-WORD INSTRUCTION DBcc DBcc DISPLACEMENT $FFFC = 4 VECTOR BASE REGISTER (VBR) MC68360 USER’S MANUAL 0 MOTOROLA ...
Page 147
... Separate User and Supervisor Stack Pointers (USP and SSP) • Separate User and Supervisor Address Spaces • Separate Program and Data Address Spaces • Many Data Types • Flexible Addressing Modes • Full Interrupt Processing • Expansion Capability MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-5 ...
Page 148
... Figure 5-3. User Programming Model 5 (USP CCR MC68360 USER’S MANUAL DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER MOTOROLA ...
Page 149
... The CPU32+ generates a function code each time it accesses an address. Spe- cific codes are assigned to each type of access. The codes can be used to select eight dedicated 4-Gbyte address spaces. The MOVEC instruction can use registers SFC and DFC to specify the function code of a memory address. MOTOROLA (SSP) ...
Page 150
... PACK, UNPK — Pack, Unpack BCD Instructions The CPU32+ traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to define special-pur- pose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements. 5-8 ...
Page 151
... LEA Load Effective Address LINK Link and Allocate LPSTOP Low-Power Stop LSL, LSR Logical Shift Left and Right MOVE Move MOTOROLA Table 5-1. Instruction Set Mnemonic MOVEA Move Address MOVE CCR Move Condition Code Register MOVE SR Move to/from Status Register MOVE USP ...
Page 152
... UNIMPLEMENTED INSTRUCTIONS. The ability to trap on unimplemented instruc- tions allows user-supplied code to emulate unimplemented capabilities or to define special- purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements. See 5.5.2.8 Illegal or Unim- plemented Instructions for more details. ...
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... Data registers, division remainder, division quotient Dx, Dy Data registers, used in computation Dym, Dyn Data registers, table interpolation values MOTOROLA A register field of the instruction contains the num- ber of the register. An effective address field of the instruction con- tains address mode information. The definition of an instruction implies the use of specific registers. MC68360 USER’ ...
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... Status register SSP Supervisor stack pointer USP User stack pointer FC Function code DFC Destination function code register SFC Source function code register Arithmetic addition or postincrement – Arithmetic subtraction or predecrement / Arithmetic division or conjunction symbol Arithmetic multiplication = Equal to 5-12 MC68360 USER’S MANUAL MOTOROLA ...
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... Integer Arithmetic Binary-Coded Decimal Arithmetic Logic Program Control Shift and Rotate System Control The complete range of instruction capabilities combined with the addressing modes de- scribed previously provide flexibility for program development. All CPU32+ instructions are summarized in Table 5-2. MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-13 ...
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... BGND BKPT # data BRA label Z; BSET Dn, eaÒ BSET # data ea (SP BSR label BTST Dn BTST # data ea CHK ea ,Dn CHK2 ea ,Rn CLR ea cc CMP ea ,Dn CMPA ea ,An CMPI # data ea cc CMPM (Ay)+,(Ax)+ MC68360 USER’S MANUAL Syntax MOTOROLA ...
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... MOVE from CCR CCR Destination MOVE to CCR Source CCR If supervisor state MOVE from SR then SR Destination else TRAP If supervisor state MOVE to SR then Source else TRAP MOTOROLA Operation CMP2 ea ,Rn Dn; DBcc Dn, label PC) DIVS.W ea ,Dn 32/16 DIVS.L ea ,Dq 32/32 Destination DIVS.L ea ,Dr:Dq 64/32 DIVSL.L ea ,Dr:Dq 32/32 DIVU.W ea ,Dn 32/16 DIVU.L ea ,Dq 32/32 Destination DIVU ...
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... MULU MULU MULU.L ea ,Dh: NBCD ea NEG ea NEGX ea NOP NOT ,Dn OR Dn, ea ORI # data , ea ORI # data ,CCR ORI # data ,SR PEA ea RESET ROd 1 Rx,Dy ROd 1 # data ,Dy ROd 1 ea ROXd 1 Rx,Dy ROXd 1 # data ,Dy ROXd 1 ea RTD # displacement RTE RTR MOTOROLA ...
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... CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that indicate the result of a processor operation. Table 5-2 lists the effect of each instruction on these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them. Refer to Table 5 example. MOTOROLA Operation SP RTS ...
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... MC68360 USER’S MANUAL Special Definition (IR < LB > UB > UB) (R < LB – MOTOROLA ...
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... CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all MOTOROLA Sm Dm ...
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... A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arith- metic operations. 5-20 MC68360 USER’S MANUAL MOTOROLA ...
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... NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The test (TST) instruction arithmetically compares the operand with zero, placing the result in the CCR. Table 5-6 summarizes the logical operations. MOTOROLA Operand Size 8, 16, 32 ...
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... Immediate Data 8, 16, 32 Source Destination 8, 16, 32 Immediate Data 8, 16, 32 Destination Destination 8, 16, 32 Source V Destination 8, 16 16, 32 Immediate Data V Destination 8, 16, 32 Source – set condition codes MC68360 USER’S MANUAL Operation Destination Destination Destination Destination Destination Destination Destination Destination MOTOROLA ...
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... All bit manipulation operations can be per- formed on either registers or memory. The bit number is specified as immediate data data register. Register operands are 32 bits, and memory operands are 8 bits. Table 5 summary of bit manipulation instructions. MOTOROLA Operand Size 8, 16, 32 ...
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... Operand Size 8 Source 10 + Destination – Destination 10 – Destination 10 – Source 10 – MC68360 USER’S MANUAL Operation Z bit bit bit of Z instructions support Operation Destination Destination Destination MOTOROLA ...
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... CCR provide system control operations. All of these instructions cause the processor to flush the instruction pipeline. Table 5-11 summa- rizes the instructions. The preceding list of condition tests also applies to the TRAPcc instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. MOTOROLA Operand Size Conditional ...
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... Condition Code Register 8 Immediate Data CCR 8 Immediate Data CCR 16 Source CCR 16 CCR Destination 8 Immediate Data V CCR MC68360 USER’S MANUAL Operation SP; (SP) PC SP; EBI; STOP – (SSP); – (SSP); (vector) PC (SSP); (SSP); (SSP); PC (SSP); (SSP); SR (SSP); CCR CCR CCR MOTOROLA ...
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... Two additional examples show how TBLSN can reduce cumulative error when multiple table lookup and interpolation operations are used in a calculation. Example 4 demonstrates addi- tion of the results of three table interpolations. Example 5 illustrates use of TBLSN in surface interpolation. MOTOROLA Table 5-12. Condition Tests Condition Encoding ...
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... X INDEPENDENT VARIABLE Figure 5-7. Table Example MC68360 USER’S MANUAL X 49152. Table Y-Value 1311 1659 1669 1679 1690 1966 65536 MOTOROLA ...
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... Table 5-14. Compressed Table Entries Entry Number Since the table is reduced from 257 to 5 entries, independent variable X must be scaled appropriately. In this case the scaling factor is 64, and the scaling is done by a single instruc- tion: LSR.W #6,Dx MOTOROLA 256 512 786 X INDEPENDENT VARIABLE Figure 5-8. Table Example 2 ...
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... The subroutine uses the data listed in Table 5-15, based on the function shown in Figure 5-9. Y 1024 5- 2048 3072 X INDEPENDENT VARIABLE Figure 5-9. Table Example 3 MC68360 USER’S MANUAL example shows 4096 MOTOROLA 0 0 ...
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... Thus calculated as follows (13 (64 – 80 the 8-bit value for X were used directly by the table instruction, interpolation would be in- correctly performed between entries 0 and 1. Data must be shifted to the left four places be- fore use: LSL.W #4, Dx MOTOROLA X X (Instruction ...
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... TBL # 1 0010 0000 . TBL # 2 0011 1111 . TBL # 3 0000 0001 . 0010 0000 . 0011 1111 . 0000 0001 . 0110 0000 . MC68360 USER’S MANUAL MOTOROLA 0 0 ...
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... The LINK instruction pushes an address onto the stack, saves the stack address at which the address is stored, and reserves an area of the stack for use. Using this instruction in a series of subroutine calls will generate a linked list of stack frames. MOTOROLA 0010 0000 . 0111 0000 0011 1111 . 0111 0000 0000 0001 ...
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... STOP or LPSTOP instruction, execution of instructions can resume when a trace, interrupt, or reset exception occurs. 5.4.2 Privilege Levels To protect system resources, the processor can operate with either of two levels of access— user or supervisor. Supervisor level is more privileged than user level. All instructions are 5-34 MC68360 USER’S MANUAL MOTOROLA ...
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... The RTE instruction causes a return to a program that was executing when an exception occurred. When RTE is executed, the exception stack frame saved on the supervisor stack can be restored in either of two ways. MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-35 ...
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... Sources of external exception include interrupts, breakpoints, bus errors, and reset requests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access control and processor restart. 5-36 MC68360 USER’S MANUAL MOTOROLA ...
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... Because there is no protection on the 64 processor-defined vec- tors, external devices can access vectors reserved for internal purposes. This practice is strongly discouraged. MOTOROLA Vector Offset Hex Space 0 000 SP Reset: Initial Stack Pointer 4 004 SP Reset: Initial Program Counter ...
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... See 5.5.4 CPU32+ Stack Frames for a complete discussion of exception stack frames FORMAT Figure 5-10. Exception Stack Frame 5-38 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION, DEPENDING ON EXCEPTION ( WORDS) MC68360 USER’S MANUAL 0 MOTOROLA ...
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... For example bus error occurs during trace exception processing, the bus error will be processed and handled before trace exception processing has completed. MOTOROLA Exception and Aborts all processing (instruction or excep- tion) ...
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... Direct assertion of the internal BERR signal by an internal module 3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog after detecting a no-response condition Bus error exception processing begins when the processor attempts to use information from an aborted bus cycle. 5-40 MC68360 USER’S MANUAL MOTOROLA ...
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... Released write bus errors are delayed until the next instruction boundary or until another operand access is attempted. Exception processing for bus error exceptions follows the regular sequence, but context preservation is more involved than for other exceptions because a bus exception can be ini- MOTOROLA ENTRY 1 S ...
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... Exception processing for traps follows the regular sequence. If tracing is enabled when an instruction that causes a trap begins execution, a trace exception will be generated by the instruction, but the trap handler routine will not be traced. (The trap exception will be pro- cessed first, then the trace exception.) 5-42 MC68360 USER’S MANUAL MOTOROLA ...
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... This check ensures that the program does not make erroneous assumptions about information in the stack frame. If the format of the control data is improper, the processor generates a format error excep- tion. This exception saves a four-word format exception frame and then vectors through vec- MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-43 ...
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... A separate F-line emulation vector (vector 11, offset $2C) is used for the exception vector. All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 family members. Those customers requiring the use of an unimplemented opcode for synthesis of " ...
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... When T1– the beginning of instruction execution, a trace exception will be gener- ated when execution is complete. If the instruction is not executed, either because an inter- rupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception is not generated. MOTOROLA Table 5-18. Tracing Control T0 Tracing Function 0 ...
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... CPU32+ At the present time, T1– undefined condition reserved by Motorola for future use. Exception processing for trace starts at the end of normal processing for the traced instruc- tion and before the start of the next instruction. Exception processing follows the regular sequence; tracing is disabled so that the trace exception itself is not traced. A vector number is generated to reference the trace exception vector ...
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... RETURN FROM EXCEPTION. When exception stacking operations for all pend- ing exceptions are complete, the processor begins execution of the handler for the last exception processed. After the exception handler has executed, the processor must restore MOTOROLA MC68360 USER’S MANUAL CPU32+ ...
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... SSW contains the internal processor state corresponding to the fault SZC1 SZC0 MC68360 USER’S MANUAL $14 in the stack frame. The SIZ FUNC MOTOROLA 0 ...
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... B0—Breakpoint Channel 0 Pending B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint source) when the bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception Breakpoint not pending 1 = Breakpoint pending MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-49 ...
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... FC2–FC0 for the faulted bus cycle. This field is reloaded into the bus controller if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored during unstacking. Further discussion of the SSW is included in 5.5.3.1 Types of Faults. 5-50 MC68360 USER’S MANUAL MOTOROLA ...
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... The SSW for faults in this category contains the following bit pattern SZC1 0 B1 The trace pending bit is always cleared since the instruction will be restarted upon return from the handler. Saving a pending exception on the stack causes a trace exception to be MOTOROLA SZC0 10 ...
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... However, if the exception is one that causes a four- or six-word stack frame to be written, a bus cycle fault frame is written below the faulted exception stack frame. 5- SZC0 MC68360 USER’S MANUAL SIZ FUNC MOTOROLA 0 ...
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... The RR bit in the SSW is checked during the unstacking operation set, the RW, FUNC, and SIZ fields are restored and the released write cycle is rerun. To maintain long-word operand coherence, stack contents must be adjusted prior to the RTE execution. The fault address must be decremented the SZCx bits are set to long MOTOROLA ...
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... set in the stacked SSW, create a six-word stack frame and execute the trace handler. If either set in the SSW, create another six-word stack frame and execute the hardware breakpoint handler. 5-54 MC68360 USER’S MANUAL MOTOROLA ...
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... Once the exception handler determines that the fault has been corrected, recovery can pro- ceed as described previously. If the fault cannot be corrected, move the supervisor stack to another area of memory, copy all valid stack frames to the new stack, create a faulted MOTOROLA MC68360 USER’S MANUAL CPU32+ $10) ...
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... The CPU32+ bus error stack frame differs significantly from the equivalent stack 5-56 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW 0 VECTOR OFFSET STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW MC68360 USER’S MANUAL 0 0 MOTOROLA ...
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... PC. (The internal transfer count register is located at SP $10 and the SSW is located at SP The fault address of a dynamically sized bus cycle is the address of the upper byte, regard- less of the byte that caused the error. MOTOROLA ...
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... SPECIAL STATUS WORD STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW PRE-EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT/VECTOR WORD INTERNAL TRANSFER COUNT REGISTER SPECIAL STATUS WORD MC68360 USER’S MANUAL MOTOROLA ...