CY7C375I-83AC Cypress Semiconductor Corporation., CY7C375I-83AC Datasheet

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CY7C375I-83AC

Manufacturer Part Number
CY7C375I-83AC
Description
CY7C375I-83ACUltraLogic 128-Macrocell Flash CPLD
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-03029 Rev. *A
Features
Selection Guide
Maximum Propagation Delay
Minimum Set-Up, t
Maximum Clock to Output
Typical Supply Current, I
Note:
• 128 macrocells in eight logic blocks
• 128 I/O pins
• Five dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
• Fully PCI compliant
1. The 3.3V I/O mode timing adder, t
— JTAG Interface
— f
— t
— t
— t
Logic Block Diagram
MAX
PD
S
CO
= 5.5 ns
I/O
I/O
I/O
= 10 ns
= 6.5 ns
I/O
= 125 MHz
16
32
48
0
–I/O
–I/O
–I/O
–I/O
15
31
47
63
S
16 I/Os
16 I/Os
16 I/Os
16 I/Os
CC
[1]
, t
[1]
3.3IO
CO
, t
PD
, must be added to this specification when V
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
4
7C375i–125 7C375i–100 7C375i–83
64
A
B
C
D
MACROCELL
125
5.5
6.5
10
INPUT
36
16
36
16
36
16
36
16
UltraLogic™ 128-Macrocell Flash CPLD
3901 North First Street
USE ULTRA37000™
FOR ALL NEW DESIGNS
Inputs
1
PIM
125
12
6
7
Inputs
Clock
4
36
16
36
16
36
16
36
16
Functional Description
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
all members of the F
designed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogic™ F
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
because of the superior routability of the F
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
INPUT/CLOCK
MACROCELLS
• 3.3V or 5.0V I/O operation
• Available in 160-pin TQFP, CQFP, and PGA packages
LASH
CCIO
125
15
8
8
= 3.3V
370i™ family of high-density, high-speed CPLDs. Like
BLOCK
LOGIC
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
64
H
G
F
E
4
7C375iL–83 7C375i–66 7C375iL–66 Unit
San Jose
15
75
8
8
16 I/Os
16 I/Os
16 I/Os
16 I/Os
LASH
,
CA 95134
LASH
370i family, the CY7C375i is
I/O
I/O
I/O
I/O
125
20
10
10
370i devices, the CY7C375i
112
96
80
64
–I/O
–I/O
–I/O
–I/O
Revised May 10, 2004
111
95
79
127
LASH
EN
CY7C375i
408-943-2600
). Additionally,
20
10
10
75
370i devices,
mA
ns
ns
ns

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CY7C375I-83AC Summary of contents

Page 1

... FOR ALL NEW DESIGNS UltraLogic™ 128-Macrocell Flash CPLD • 3.3V or 5.0V I/O operation • Available in 160-pin TQFP, CQFP, and PGA packages Functional Description The CY7C375i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the F 370i™ family of high-density, high-speed CPLDs. Like LASH ...

Page 2

... CCIO 40 Document #: 38-03029 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Top View TQFP CY7C375i V 120 CCIO I/O 119 111 118 I/O 110 117 I/O 109 116 I/O /SDI 108 I/O 115 107 I/O 114 106 113 I/O 105 112 I/O 104 ...

Page 3

... Document #: 38-03029 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Top View CQFP CY7C375i 120 V CC 119 I/O 111 118 I/O 110 117 I/O 109 I/O /SDI 116 108 I/O 115 107 I/O 114 106 I/O 113 105 I/O 112 104 ...

Page 4

... Like all members of the F 370i family, the CY7C375i is rich LASH in I/O resources. Every macrocell in the device features an associated I/O pin, resulting in 128 I/O pins on the CY7C375i. In addition, there is one dedicated input and four input/clock pins. Finally, the CY7C375i features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays ...

Page 5

... I/O pin is used as an input. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C375i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...

Page 6

... Max Max. CC Test Conditions V = 5.0V at f=1 MHz 5. MHz CCINT pin Max. EN CY7C375i Ambient Temperature CCINT 5V ± 0.25V 5V ± 0.25V or 0°C to +70°C 3.3V ± 0.3V −40°C to +85°C 5V ± 0.5V 5V ± 0.5V or 3.3V ± 0.3V –55°C to +125°C 5V ± 0.5V Min. ...

Page 7

... JIG AND (b) SCOPE 2.08V(COM'L) 2.13V(MIL) V Output Waveforms--Measurement Level X 1. 0.5V 2.6V 0. 1.5V 0. the V X 0.5V (d) Test Waveforms measured with 35-pF AC Test Load. EA CY7C375i 160-Lead 160-Pin 160-Pin TQFP CQFP CPGA Max. 100 ALL INPUT PULSES 3.0V 90% 10% GND <2ns Unit nH ...

Page 8

... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...

Page 9

... Min. 8 125 100 , 1/( ICS WL WH [9] 10 [9] 12 [1] 16 [9] 10 [9] 12 [1] 16 500 500 CY7C375i 7C375i–83 7C375i–66 7C374iL–83 7C375iL–66 Max. Min. Max. Min 83.3 66 500 500 1 ...

Page 10

... INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Document #: 38-03029 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS PDL ICS CY7C375i ICO SCS Page ...

Page 11

... Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: 38-03029 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS PDL ICOL t ICS t WH CY7C375i t ICO PDLL Page ...

Page 12

... INPUT OUTPUTS Ordering Information Speed (MHz) Ordering Code 125 CY7C375i–125AC 100 CY7C375i–100AC CY7C375i–100AI 83 CY7C375i–83AC CY7C375i–83AI CY7C375i–83GMB CY7C375i–83UMB CY7C375iL–83AC Document #: 38-03029 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS ...

Page 13

... Ordering Information (continued) Speed (MHz) Ordering Code 66 CY7C375i–66AC CY7C375i–66AI CY7C375i–66GMB CY7C375i–66UMB CY7C375iL–66AC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter ...

Page 14

... Package Diagrams 160-Pin Thin Plastic Quad Flat Pack ( 1.4 mm)(TQFP) A160 Document #: 38-03029 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C375i 51-85049-*B Page ...

Page 15

... Package Diagrams (continued) Document #: 38-03029 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS 160-Pin PGA G160 CY7C375i 51-80012-*A Page ...

Page 16

... USE ULTRA37000™ FOR ALL NEW DESIGNS 25.35±0.10 (.998±.004) TYP. 28.00 ±0.10 (1.102 ±.004) SQ. 31.20 ±0.25 (1.228 ±.010) SQ. SEE DETAIL A CY7C375i DIMENSION IN MM (INCH) REFERENCE JEDEC: N/A PKG. WEIGHT: 6-7gms 0.650(.0256) TYP. 0.300(.012) TYP. R 0.13(.005) MIN. 0°-7° 0.20 MIN. ...

Page 17

... Document History Page Document Title: CY7C375i UltraLogic™ 128-Macrocell Flash CPLD Document Number: 38-03029 REV. ECN NO. Issue Date ** 106374 09/15/01 *A 213375 See ECN Document #: 38-03029 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Orig. of Change SZV Change from Spec number: 38-00494 to 38-03029 FSG Added note to title page: “ ...

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