M5M54R16ATP-12 MITSUBISHI, M5M54R16ATP-12 Datasheet

M5M54R16ATP-12

Manufacturer Part Number

M5M54R16ATP-12

Description

4194304-bit (262144-word by 16-bit) CMOS static RAM

Manufacturer

MITSUBISHI

Datasheet

1.M5M54R16ATP-10.pdf (7 pages)

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

M5M54R16ATP-12

Manufacturer:

MIT

Quantity:

3 590

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•Fast access time

•Single +3.3V power supply

•Fully static operation : No clocks, No refresh

•Common data I/O

•Easy memory expansion by S

•Three-state outputs : OR-tie capability

•OE prevents data contention in the I/O bus

•Directly TTL compatible : All inputs and outputs

•Separate control of lower and upper bytes by LB and UB

FEATURES

DESCRIPTION

The M5M54R16A is a family of 262144-word by 16-bit

static RAMs, fabricated with the high performance CMOS

process and designed for high speed application. These

devices operate on a single 3.3V supply, and are directly

TTL compatible.

and read cycles, the lower and upper bytes are able

to be controled either togethe or separately by LB

and UB.

High-speed memory system

by a combination of the device control inputs S, W, OE,

LB, and UB. Each mode is summarized in the function

table.

overlaps with low level LB and/or low level UB and low

level S. The address must be set-up before write cycle

and must be stable during the entire cycle.

W, LB, UB or S, whichever occurs first, requiring the

set-up and hold time relative to these edge to be

maintained. The output enable input OE directly

controls the output stage. Setting the OE at a high level,

the output stage is in a high impedance state, and the

data bus contention problem in the write cycle is

eliminated.

and OE at a low level while LB and/or UB and S are in

an active

APPLICATION

FUNCTION

The operation mode of the M5M54R16A is determined

They include a power down feature as well. In write

A write cycle is executed whenever the low level W

A read cycle is excuted by setting W at a high level

PRELIMINARY

The data is latched into a cell on the traling edge of

Notice: This is not a final specification.

Some parametric limits are subject to change.

M5M54R16AJ,ATP-12 ... 12ns(max)

M5M54R16AJ,ATP-15 ... 15ns(max)

M5M54R16AJ,ATP-10 ... 10ns(max)

1998.11.30 Ver.B

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI

ELECTRIC

M5M54R16AJ,ATP-10,-12,-15

PACKAGE

state. (LB and/or UB=L, S=L)

an active state, upper-Byte are in a selectable mode

in which both reading and writing are enable, and

lower-Byte are in a non-selectable mode. And when

setting UB at a high level and other pins are in an

active state, lower-Byte are in a selectable mode in

which both reading and writing are enable, and upper-

Byte are in a non-selectable mode.

level, the chip is in a non-selectable mode in which

both reading and writing are disabled. In this mode,

the output stage is in a high-impedance state,

allowing OR-tie with other chips and memory

expansion by LB, UB and S.

goes high, power dissapation is reduced extremely.

The access time from S is equivalent to the address

access time.

When setting LB at a high level and other pins are in

When setting LB and UB at a high level or S at high

Signal-S controls the power-down feature. When S

M5M54R16AJ

M5M54R16ATP .......... 44pin 400mil TSOP(II)

CONTROL INPUT

CHIP SELECT

ADDRESS

PIN CONFIGURATION (TOP VIEW)

DATA

OUTPUTS

DATA

OUTPUTS

INPUTS/

WRITE

INPUTS

INPUT

(3.3V)

(0V)

GND

Outline

.......... 44pin 400mil SOJ

44P0K

MITSUBISHI LSIs

GND

N.C

ENABLE INPUT

ADDRESS

(3.3V)

OUTPUTS

ADDRESS

CONTROL

DATA

INPUTS/

OUTPUT

DATA

INPUTS/

(0V)

INPUTS

BYTE

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M5M54R16ATP-12 Summary of contents

Page 1

... Outline PACKAGE M5M54R16AJ .......... 44pin 400mil SOJ M5M54R16ATP .......... 44pin 400mil TSOP(II) state. (LB and/or UB=L, S=L) When setting high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when ...

Page 2

... ROWS 4096 COLUMNS COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS COLUMN INPUT BUFFERS ADDRESS INPUTS MITSUBISHI ELECTRIC MITSUBISHI LSIs DQ1~8 DQ9~ OUT OUT D OUT D High-impedance OUT High-impedance IN High-impedance High-impedance A ...

Page 3

... CC Z0=50 OUTPUT V =3.0V,V =0. 3ns V =1.5V,V =1. =1.5V, V =1. Fig1 ,Fig2 Fig.1 Output load MITSUBISHI ELECTRIC MITSUBISHI LSIs Unit * 1000 °C °C °C +10% ,unless otherwise noted) -5% Limits Min Typ Max 2.0 Vcc+0.3 0.8 2.4 AC(10ns cycle) 260 AC(12ns cycle) 250 ...

Page 4

... MITSUBISHI ELECTRIC MITSUBISHI LSIs Unit Max Min Max ...

Page 5

... Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM (A) tv (A) UNKNOWN LB=L UB (S) (Note 4) ten (S) UNKNOWN t PU 50% UB=L LB (OE) (Note 4) ten (OE) UNKNOWN UB=L LB=L MITSUBISHI ELECTRIC MITSUBISHI LSIs tv (A) DATA VALID (Note 4) t dis (S) DATA VALID t PD 50% (Note 4) t dis (OE) DATA VALID 5 ...

Page 6

... BY 16-BIT) CMOS STATIC RAM (B) (Note 4) ten (B) UNKNOWN OE tsu (S) tsu (A-WH) tsu trec t w (A) (W) tsu (B) tsu th (D) (D) DATA STABLE t dis (Note 4) (W) t dis (OE) Hi-Z MITSUBISHI ELECTRIC MITSUBISHI LSIs (Note 4) t dis (B) DATA VALID (Note 7) (W) (Note 7) ten (Note 4) (OE) ten (W) 6 ...

Page 7

... OH Hi-Z OL (Note tsu ( (Note tsu (Note 6) (A-BH) tsu (B) tsu ( tsu (D) IH DATA STABLE IL t dis (W) (Note 4) (Note 4) ten (S) ten (B) OH Hi-Z OL (Note 8) MITSUBISHI ELECTRIC MITSUBISHI LSIs trec (W) (Note 6) (Note 6) th (D) (Note 6) (Note 6) trec (W) th (D) 7 ...

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