AD807-155BR Analog Devices, AD807-155BR Datasheet
AD807-155BR
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AD807-155BR Summary of contents
Page 1
... Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, C put frequency to the VCO center frequency. The AD807 consumes 140 mW and operates from a single power supply at either + –5.2 V. FUNCTIONAL BLOCK DIAGRAM QUANTIZER ...
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... AD807–SPECIFICATIONS Parameter QUANTIZER–DC CHARACTERISTICS Input Voltage Range Input Sensitivity, V SENSE Input Overdrive Input Offset Voltage Input Current Input RMS Noise Input Pk-Pk Noise QUANTIZER–AC CHARACTERISTICS Upper –3 dB Bandwidth Input Resistance Input Capacitance Pulse Width Distortion LEVEL DETECT Level Detect Range ...
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... Figure 2. Setup and Hold Time Model AD807-155BR or AD807A-155BR AD807-155BR-REEL7 or AD807A-155BRRL7 AD807-155BR-REEL or AD807A-155BRRL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD807 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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... This is the frequency at which the VCO will oscillate with the loop damping capacitor shorted. D Tracking Range This is the range of input data rates over which the AD807 will remain in lock. Capture Range This is the range of input data rates over which the AD807 will acquire lock. ...
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... Acquisition Time This is the transient time, measured in bit periods, required for the AD807 to lock onto input data from its free-running state. Symmetry—Recovered Clock Duty Cycle Symmetry is calculated as (100 on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its “ ...
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... AD807–Typical Characteristic Curves 200.0E+3 180.0E+3 160.0E+3 140.0E+3 120.0E+3 100.0E+3 80.0E+3 60.0E+3 40.0E+3 20.0E+3 0.0E+0 000.0E+0 5.0E–3 10.0E–3 15.0E–3 20.0E–3 SIGNAL DETECT LEVEL – Volts Figure 6. Signal Detect Level vs. R 35.0E– THRESH 30.0E–3 25.0E–3 20.0E–3 15.0E–3 10.0E– 49.9k THRESH 5.0E–3 R THRESH 000.0E+0 –40 – TEMPERATURE – C Figure 7 ...
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... Sensitivity is achieved. Traditionally, high speed compara- tors are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD807 quantizer toggles at 650 V (1.3 mV sensitivity) at the input without making bit errors. When the input signal is lowered below 650 V, circuit performance is dominated by input noise, and not crosstalk ...
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... For example, with a damping ratio of 10, the jitter peaking is 0.02 dB, but with a damping ratio of 1, the peaking is 2 dB. Center Frequency Clamp (Figure 19) An N-channel FET circuit can be used to bring the AD807 1 VCO center frequency to within 10% of 155 MHz when S SDOUT indicates a Loss of Signal (LOS) ...
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... VECTOR PINS SPACED THROUGH-HOLE CAPACITOR ON VECTOR CUPS; COMPONENT SHOWN FOR REFERENCE ONLY Figure 21. Evaluation Board Schematic INT2 08-002901-08 REV A COMPONENT SIDE 08-002901-01 REV A Figure 22. Evaluation Board Pictorials –9– AD807 SDOUT C12 0.1µF R13 R16 3.65k 301 R14 R15 C13 0.1µF 49.9 49.9 J6 ...
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... Loses Lock APPLICATIONS Low Cost 155 Mbps Fiber Optic Receiver The AD807 and AD8015 can be used together for a complete 155 Mbps Fiber Optic Receiver (Quantizer and Clock Recovery, and Transimpedance Amplifier) as shown in Figure 23. The PIN diode front end is connected to a single mode 1300 nm laser source ...
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... CD 0.1µF C6 0.1µF Figure 26. AD807 Application with Epitaxx PIN—Transimpedance Amplifier Module The entire circuit was enclosed in a shielded box. Table I sum- marizes results of tests performed using a 2 and varying the average power at the PIN diode. The circuit acquires and maintains lock with an average input power as low as – ...
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... Using a 0.15 F, +20% capacitor for a damping factor of five provides < 0.1 dB jitter peaking. PIN 1 0.0098 (0.25) 0.0040 (0.10) AD807 Output Squelch Circuit A simple P-channel FET circuit can be used in series with the Output Signal ECL Supply (V data outputs when SDOUT indicates a loss of signal (Figure 29). The V CC2 of 4 ECL loads, plus 5 mA for all 4 ECL output stages) ...