GTLP16T1655 Fairchild Semiconductor, GTLP16T1655 Datasheet

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GTLP16T1655

Manufacturer Part Number
GTLP16T1655
Description
GTLP16T165516-Bit LVTTL/GTLP Universal Bus Transceiver
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2000 Fairchild Semiconductor Corporation
GTLP16T1655MTD
GTLP16T1655
16-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP16T1655 is a 16-bit universal bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface
between cards operating at LVTTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing ( 1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver Logic (GTL) JEDEC standard
JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
MTD64
64-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide
DS500172
Features
Bidirectional interface between GTLP and LVTTL logic
levels
Variable Edge Rate Control pin to select desired edge
rate on the GTLP backplane (V
Partitioned as two 8-Bit transceivers with individual latch
timing and output control but with a common clock.
Power up/down high impedance for live insertion.
External pin to pre-condition I/O capacitance to high
state
Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs
LVTTL compatible driver and control inputs
Flow through pinout optimizes PCB layout
Open drain on GTLP to support wired-or connection
A Port source/sink 24 mA/ 24 mA
B Port sink 100mA
D-type flip-flop, latch and transparent data paths
Available in TSSOP
40 C to 85 C Temperature capability
Package Description
August 1998
Revised April 2000
ERC
)
www.fairchildsemi.com

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GTLP16T1655 Summary of contents

Page 1

... GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver General Description The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a back- plane operating at GTLP logic levels. High speed back- plane operation is a direct result of GTLP’ ...

Page 2

Connection Diagram Truth Tables (Note 1) Inputs CEAB LEAB Inputs OE OEAB OEBA ...

Page 3

... Functional Description The GTLP16T1655 is a high drive (100 mA) 16-bit univer- sal bus transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. The device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output control signals but with a common clock pin (CLK) for both transceiver words ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 5) DC Output Sink Current into A Port Output Source Current from ...

Page 5

DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, V Symbol V B Port IH Others V B Port IL Others V GTLP REF Port V Min to Max (Note ...

Page 6

Live Insertion Characteristics Over Recommended Operating Free-Air Temperature Range, V Parameter I B Port BIAS) V 3 Port BIAS ...

Page 7

Electrical Characteristics (GTLP) Over recommended range of supply voltage and operating free air temperature, V B-Port and for A-Port. L From Symbol (Input) f MAX t A PLH PHL ERC ...

Page 8

Extended Electrical Characteristics (GTLP) Over recommended ranges of supply voltage and operating free-air temperature for B Port and for A Port Symbol t (Note 14) OSLH t (Note 14) OSHL t ...

Page 9

AC Operating Requirements (GTL) Over recommended ranges of supply voltage and operating free-air temperature, V Parameter f Max Clock Frequency CLOCK t Pulse Duration WIDTH t Setup Time SU t Hold Time HOLD Electrical Characteristics (GTL) ...

Page 10

Electrical Characteristics (GTL) Over recommended range of supply voltage and operating free air temperature for B Port and for A Port From Symbol (Input) f MAX t ...

Page 11

Extended Electrical Characteristics (GTL) Over recommended ranges of supply voltage and operating free-air temperature for B Port and for A Port Symbol (Input) t (Note 20) OSLH t (Note 20) OSHL ...

Page 12

Test Circuits and Timing Waveforms Test Circuit for A Outputs Test Open PLH PHL PLZ PZL t /t GND PHZ PZH Voltage Waveform - Propagation Delay Times Voltage Waveform - Pulse Width V V ...

Page 13

Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide Package Number MTD64 13 www.fairchildsemi.com ...

Page 14

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE ...

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