HY27UG084G2M Hynix Semiconductor, HY27UG084G2M Datasheet

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Document Title 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Add Errata tWH 0.1 Specification 15 Relaxed value 20 1) Correct the Valid Blocks Number. Valid Blocks (max) 0.2 Before 4,098 After 4,096 ...

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Revision History Revision No. 7) Correct PKG dimension (TSOP PKG) CP Before 0.050 After 0.100 8) Delete the 1.8V device’s features. 9) Change DC Characteristics (Table 8) - Operating Current I CC1 Typ Max Before 20 40 After 25 45 ...

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Revision History Revision No. 1) Correct tCS parameter in Autosleep tCS 0.7 Before 100ns (Min.) After 40ns (Min.) Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash History -Continued- Draft Date Remark Feb. 14. 2006 3 ...

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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = 2.7 to ...

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SUMMARY DESCRIPTION The HYNIX HY27UG(08/16)4G(2/D)M series is a 512Mx8bit with spare 16Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The ...

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IO8 - IO15 IO7 - IO0 CLE ALE R/B Vcc Vss NC PRE Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 only) Data ...

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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 7 ...

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Figure 3. 52-ULGA Contactions, x8 Device, Dual interface Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash (Top view through package) 8 ...

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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program IO0-IO7 operations. The inputs are latched on the rising edge of Write Enable (WE). The ...

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IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 5th Cycle A28 Table 3: Address Cycle Map(x8) NOTE must be set to Low. IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th ...

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CLE ALE ( NOTE: 1. With ...

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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...

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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with five address cycles. In two consecutive read ...

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Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A18 to A29 (X8) or A17 to A28 (X16) is valid ...

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Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 00h(don’t ...

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Cache Read Cache read operation allows automatic download of consecutive pages the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page ...

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OTHER FEATURES 4.1 Data Protection & Power On/Off Sequence. The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides ...

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Unlock - Command Sequence: Unlock block Command (23h) + Start block address + Command (24h) + End block address. See Fig. 24. - Unlocked blocks can be programmed or erased unlocked block’s status can be changed to ...

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Parameter Symbol Valid Block Number N VB Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient Operating Temperature (Industrial Temperature Range) T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or ...

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Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 4: Block Diagram 20 ...

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Parameter Symbol Sequential I CC1 Read Operating Current Program I CC2 Erase I CC3 Stand-by Current (TTL) I CC4 Stand-by Current (CMOS) I CC5 Input Leakage Current I LI Output Leakage Current I LO Input High Voltage V IH Input ...

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Item Input / Output Capacitance Input Capacitance Table 10: Pin Capacitance (TA=25℃, F=1.0MHz) Parameter Program Time Dummy Busy Time for Cache Program Dummy Busy Time for Cache Read Dummy Busy Time for the Lock or Lock-tight Block Number of partial ...

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Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time ALE to Data Loading Time ...

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Page Block IO Program Erase 0 Pass / Fail Pass / Fail Ready/Busy Ready/Busy 6 Ready/Busy Ready/Busy 7 Write Protect Write Protect Table 13: Status Register Coding ...

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... Reserved reserved 64K Block Size 128K (Without Spare Area) 256K Reserved X8 Organization X16 Table 15: 4th Byte of Device Identifier Description Part Number Voltage Bus Width HY27UG084G2M 3.3V HY27UG084GDM 3.3V HY27UG164G2M 3.3V Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash IO7 IO6 IO5 ...

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Figure 5: Command Latch Cycle Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Table 17: Lock Status Code 26 ...

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Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 6: Address Latch Cycle 27 ...

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Figure 7. Input Data Latch Cycle Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 28 ...

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Figure 10: Read1 Operation (Read One Page) Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 9: Status Read Cycle 29 ...

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Figure 11: Read1 Operation intercepted by CE Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 30 ...

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Figure 12 : Random Data output Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 31 ...

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Figure 13: Page Program Operation Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 32 ...

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Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 14 : Random Data In 33 ...

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Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 15 : Copy Back Program 34 ...

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Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 16 : Cache Program 35 ...

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Figure 17: Block Erase Operation (Erase One Block) Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 18: Read ID Operation 36 ...

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Figure 19: start address at page start :after 1st latency uninterrupted data flow Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 37 ...

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Figure 20: exit from cache read in 5us when device internally is reading Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 38 ...

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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microporcessor. The only function that was removed ...

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Figure 24: Unlock Command Sequence Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 23: Lock Command 40 ...

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Figure 25: Lock Tight Command Figure 26: Lock Status Read Timing Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 41 ...

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Figure 27: Automatic Read at Power On Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 28: Reset Operation 42 ...

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Figure 29: Power On/Off Timing VTH = 2.5 Volt for 3.3 Volt Supply devices Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 43 ...

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Figure 30: Ready/Busy Pin electrical specifications Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 44 ...

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Figure 31: Lock/Unlock FSM Flow Cart Figure 32: page programming within a block Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash 45 ...

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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...

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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 34~37) Figure 34: Enable Programming Figure 35: Disable Programming Rev 0.7 / ...

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Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 36: Enable Erasing Figure 37: Disable Erasing 48 ...

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APPENDIX : Extra Features 5.1 Automatic Page0 Read after Power Up The timing diagram related to this operation is shown in Fig. 27 Due to this functionality the CPU can directly download the boot loader from the first page ...

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Figure 38. 48-pin TSOP1 20mm, Package Outline Symbol alpha Table 19: 48-pin TSOP1 , 12 x 20mm, Package Mechanical Data Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series ...

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Figure 39. 52-ULGA 17mm, Package Outline Symbol CP1 CP2 Table 20: 52-ULGA 17mm, Package Mechanical Data Rev 0.7 / Feb. 2006 HY27UG(08/16)4G(2/D)M Series 4Gbit ...

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MARKING INFORMATION - ...

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Application Note 1. Power-on/off Sequence After power is on, the device starts an internal circuit initialization when the power supply voltage reaches a specific level. The device shows its internal initialization status with the Ready/Busy signal if initialization is on ...

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Automatic sleep mode for low power consumption The device provides the automatic sleep function for low power consumption. The device enters the automatic sleep mode by keeping CE at VIH level for 10us without any additional command input, and ...