K4E640411D-JC50 Samsung, K4E640411D-JC50 Datasheet

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K4E640411D-JC50

Manufacturer Part Number
K4E640411D-JC50
Description
K4E640411D-JC5016M x 4bit CMOS Dynamic RAM with Extended Data Out
Manufacturer
Samsung
Datasheet
K4E660411D, K4E640411D
• Performance Range
This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -50, or -60), package type (SOJ or TSOP-
II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
This 16Mx4 EDO Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power
consumption and high reliability.
FEATURES
• Part Identification
• Refresh Cycles
* Access mode & RAS only refresh mode
• Active Power Dissipation
K4E660411D*
K4E640411D
Speed
CAS-before-RAS & Hidden refresh mode
- K4E660411D-JC(5.0V, 8K Ref., SOJ)
- K4E640411D-JC(5.0V, 4K Ref., SOJ)
- K4E660411D-TC(5.0V, 8K Ref., TSOP)
- K4E640411D-TC(5.0V, 4K Ref., TSOP)
: 8K cycle/64ms
: 4K cycle/64ms
-50
-60
Speed
-50
-60
Part
NO.
50ns
60ns
t
RAC
Refresh
13ns
15ns
cycle
16M x 4bit CMOS Dynamic RAM with Extended Data Out
t
495
440
CAC
8K
8K
4K
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
104ns
84ns
t
RC
Refresh time
Normal
64ms
660
605
Unit : mW
4K
20ns
25ns
t
PC
DESCRIPTION
(A0~A11)*1
(A0~A11)*1
A0~A12
A0~A10
RAS
CAS
W
FUNCTIONAL BLOCK DIAGRAM
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +5.0V 10% power supply
Note) *1 : 4K Refresh
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
16,777,216 x 4
Memory Array
Row Decoder
Cells
CMOS DRAM
Vcc
Vss
Data out
Data in
Buffer
Buffer
OE
DQ0
DQ3
to

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K4E640411D-JC50 Summary of contents

Page 1

... This 16Mx4 EDO Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURES • Part Identification - K4E660411D-JC(5.0V, 8K Ref., SOJ) - K4E640411D-JC(5.0V, 4K Ref., SOJ) - K4E660411D-TC(5.0V, 8K Ref., TSOP) - K4E640411D-TC(5.0V, 4K Ref., TSOP) • Active Power Dissipation Unit : mW Speed 8K 4K -50 ...

Page 2

... A0 - A11 Address Inputs(4K Product) DQ0 - 3 Data In/Out V Ground SS RAS Row Address Strobe CAS Column Address Strobe W Read/Write Input OE Data Output Enable V Power(+5.0V) CC N.C No Connection CMOS DRAM • K4E660411D-T • K4E640411D DQ3 3 30 DQ2 CAS ...

Page 3

... K4E660411D, K4E640411D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...

Page 4

... K4E660411D, K4E640411D DC AND OPERATING CHARACTERISTICS Symbol Power Speed -50 I Don t care CC1 -60 I Normal Don t care CC2 -50 I Don t care CC3 -60 -50 I Don t care CC4 -60 I Normal Don t care CC5 -50 I Don t care CC6 - Operating Current (RAS and CAS, Address cycling @ ...

Page 5

... K4E660411D, K4E640411D CAPACITANCE (T = Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ3] AC CHARACTERISTICS ( Test condition : V =5.0V 10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.0/0.8V CC Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS ...

Page 6

... K4E660411D, K4E640411D AC CHARACTERISTICS (Continued) Parameter Data hold time Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) ...

Page 7

... K4E660411D, K4E640411D TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time ...

Page 8

... K4E660411D, K4E640411D NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved (min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between (min) and V (max) and are assumed to be 2ns for all inputs ...

Page 9

... K4E660411D, K4E640411D READ CYCLE RAS CRP CAS ASR ROW A ADDRESS DQ0 ~ DQ3( RAS t CSH t t RCD RSH t CAS t RAD t RAL t t RAH ASC t CAH COLUMN ADDRESS t RCS ...

Page 10

... K4E660411D, K4E640411D WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR ROW A ADDRESS DQ0 ~ DQ3( RAS t CSH t t RCD RSH t CAS t RAD t RAL t t RAH ...

Page 11

... K4E660411D, K4E640411D WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR ROW A ADDRESS DQ0 ~ DQ3( RAS t CSH t t RCD RSH t CAS t RAD t RAL t t RAH ...

Page 12

... K4E660411D, K4E640411D READ - MODIFY - WRITE CYCLE RAS CRP CAS ASR RAH ROW A ADDR DQ0 ~ DQ3( I/ I/OL t RWC t RAS t t RCD RSH t t RAD t t ASC CAH COLUMN ADDRESS t AWD ...

Page 13

... K4E660411D, K4E640411D HYPER PAGE READ CYCLE RAS CRP CAS RAD t t ASR RAH ROW A ADDR DQ0 ~ DQ3( RASP ¡ó t CSH t t HPC HPC RCD t t CAS ...

Page 14

... K4E660411D, K4E640411D HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR RAH ROW A ADDR DQ0 ~ DQ3( RASP ¡ó t HPC t t RCD ...

Page 15

... K4E660411D, K4E640411D HYPER PAGE READ-MODIFY-WRITE CYCLE RAS CRP t RCD CAS RAD t RAH t ASR t ASC ROW ADDR DQ0 ~ DQ3( I/ I/OL t RASP t CSH CAS t CAH t ASC COL. ADDR ADDR t RCS t CWL ...

Page 16

... K4E660411D, K4E640411D HYPER PAGE READ AND WRITE MIXED CYCLE RAS CAS t RAD RAH t t ASR ROW A ADDR DQ0 ~ DQ3( I/ I/OL t RASP t t READ( ) READ( ) CAC CPA t HPC CAS ...

Page 17

... K4E660411D, K4E640411D RAS - ONLY REFRESH CYCLE* NOTE : W, OE Don t care OPEN OUT RAS CRP CAS ASR RAH ROW A ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : Don t care RAS RPC t CP ...

Page 18

... K4E660411D, K4E640411D HIDDEN REFRESH CYCLE ( READ ) RAS CRP CAS ASR ROW A ADDRESS DQ0 ~ DQ3( Hidden refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. ...

Page 19

... K4E660411D, K4E640411D HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR ROW A ADDRESS DQ0 ~ DQ3( RAS t t RCD RSH t RAD t RAL t t RAH ASC t CAH ...

Page 20

... K4E660411D, K4E640411D CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE Don t care RAS RPC CAS DQ0 ~ DQ3(7) CEZ TEST MODE IN CYCLE NOTE : Don t care RAS RPC CAS ...

Page 21

... K4E660411D, K4E640411D PACKAGE DIMENSION 32 SOJ 400mil #32 #1 0.841 (21.36) 0.820 (20.84) 0.830 (21.08) 0.0375 (0.95) 0.050 (1.27) 32 TSOP(II) 400mil 0.841 (21.35) 0.821 (20.85) 0.829 (21.05) 0.037 (0.95) 0.050 (1.27) MAX 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) MAX 0.047 (1.20) MAX 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50) CMOS DRAM Units : Inches (millimeters) 0.006 (0.15) 0.012 (0.30) 0.027 (0.69) MIN Units : Inches (millimeters) ...

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