M58LW032C90ZA6 STMicroelectronics, M58LW032C90ZA6 Datasheet
M58LW032C90ZA6
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M58LW032C90ZA6 Summary of contents
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FEATURES SUMMARY WIDE x16 DATA BUS for HIGH BANDWIDTH SUPPLY VOLTAGE – 2.7 to 3.6V core supply voltage for Pro- DD gram, Erase and Read operations – 1 for I/O Buffers DDQ DD SYNCHRONOUS/ASYNCHRONOUS ...
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M58LW032C TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M58LW032C Reserved (SR0 ...
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Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Program Erase Enable input V Smart Protection, which allows protected blocks to be permanently locked. This feature is not described in the datasheet for security reasons. Please contact STMicroelectronics for further details. 128 bit Protection Register, divided into two 64 bit segments: the first contains a unique device number written by ST, the second is user programmable ...
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Figure 2. Logic Diagram DDQ 21 A1-A21 V PEN W E M58LW032C SSQ Table 1. Signal Names A1-A21 DQ0-DQ15 STS DQ0-DQ15 RP V STS ...
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M58LW032C Figure 3. TSOP56 Connections 8/ A21 A20 A19 A18 A17 A16 V DD A15 A14 A13 A12 M58LW032C V PEN A11 A10 ...
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Figure 4. TBGA64 Connections (Top view through package DQ8 DQ1 F K DQ0 PEN A13 A9 E ...
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M58LW032C Figure 5. Block Addresses Total Mbit Blocks Note: Also see Appendix A, Table 25 for a full listing of the Block Addresses. 10/61 Word (x16) Bus Width 1FFFFFh 1 Mbit or 64 KWords 1F0000h 1EFFFFh 1 ...
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SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram and Table 11, Signal Names, for a brief overview of the signals connect this device. Address Inputs (A1-A21). The Address Inputs are used to select the cells to access in the ...
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M58LW032C dicates that the data is not, or will not be valid. Val- id Data Ready in a high-impedance state indicates that valid data is or will be available. Unless Synchronous Burst Read has been select- ed, Valid Data Ready ...
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BUS OPERATIONS There are six standard bus operations that control the device. These are Address Latch, Bus Read, Bus Write, Output Disable, Power-Down and Standby. See Table 2, Bus Operations, for a sum- mary. Typically glitches of less than 5ns ...
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M58LW032C READ MODES Read operations can be performed in two different ways depending on the settings in the Configura- tion Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchro- nous; if the ...
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CR2-CR0). In Synchronous Continuous Burst Read mode one Burst Read operation can access the entire memory sequentially. If the starting ad- dress is not associated with a page (4 Word) boundary the Valid Data Ready, R, output goes Low, ...
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M58LW032C CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. The Configuration Register bits are de- scribed in Table 3. They specify the selection of the burst length, burst ...
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Table 3. Configuration Register Address Mnemonic Bit Name Bit 16 CR15 Read Select 15 CR14 14 to CR13-CR11 X-Latency 12 Internal 11 CR10 Clock Divider 10 CR9 Y-Latency Valid Data 9 CR8 Ready 8 CR7 Burst Type Valid Clock 7 ...
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M58LW032C Table 4. Burst Type Definition Starting x4 x4 Address Sequential Interleaved 0 0-1-2-3 0-1-2-3 1 1-2-3-0 1-0-3-2 2 2-3-0-1 2-3-0-1 3 3-0-1-2 3-2-1-0 4 – – 5 – – 6 – – 7 – – 8 – – Figure ...
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Figure 7. Burst Configuration X-2-2 ADD VALID L DQ 5-2-2-2 DQ 6-2-2-2 DQ 7-2-2-2 DQ 8-2-2 VALID NV NV=NOT VALID M58LW032C VALID NV VALID NV VALID NV ...
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M58LW032C COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. The Commands are summarized in Table 5, Commands. Refer to Table 5 ...
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If the block being programmed is protected an er- ror will be set in the Status Register and the oper- ation will abort without affecting the data in the memory array. The block must be unprotected us- ing the Blocks ...
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M58LW032C Read mode and the valid Clock edge configura- tion. Two Bus Write cycles are required to issue the Set Configuration Register command. Once the com- mand is issued the memory returns to Read mode Read Memory ...
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Table 5. Commands Command Read Memory Array 2 Read Electronic Signature 2 Read Status Register 2 Read Query 2 Clear Status Register 1 Block Erase 2 Word Program 2 Write to Buffer and Write Program Program/Erase Suspend ...
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M58LW032C Table 6. Configuration Codes Configuration DQ1 DQ2 Code 00h 0 0 Ready/Busy Pulse on Erase 01h 0 1 complete Pulse on 02h 1 0 Program complete Pulse on Erase 03h Program complete Note: 1. DQ2-DQ7 are ...
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Figure 8. Protection Register Memory Map WORD ADDRESS 88h 85h 84h 81h 80h Table 9. Program, Erase Times and Program Erase Endurance Cycles Parameters Block (1Mb) Erase Chip Program (Write to Buffer) Chip Erase Time Program Write Buffer Word/Byte Program ...
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M58LW032C STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. ...
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Depending on the cause of the failure other Status Register bits may also be set to High only the Program Status bit (SR4) is set High then the Program/Erase Controller has OH applied the maximum ...
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M58LW032C Table 10. Status Register Bits OPERATION Program/Erase Controller active Write Buffer not ready Write Buffer ready Write Buffer ready in Erase Suspend Program suspended Program suspended in Erase Suspend Program/Block Protect completed successfully Program completed successfully in Erase Suspend ...
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... V Input or Output Voltage Supply Voltage DD DDQ not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect de- vice reliability. STMicroelectronics SURE Program and other rel- evant quality documents. Parameter M58LW032C Refer also to Value Unit Min Max –40 125 ° ...
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M58LW032C DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from tests ...
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Table 14. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Random Read Supply Current (Burst Read) DDB I Supply Current (Standby) DD1 I Supply Current (Auto Low-Power) DD5 I ...
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M58LW032C Figure 11. Asynchronous Bus Read AC Waveforms A1-A21 DQ0-DQ15 Note: Asynchronous Read CR15 = 1 Table 15. Asynchronous Bus Read AC Characteristics. Symbol t Address Valid to Address Valid AVAV t Address Valid to Output Valid ...
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Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms A1-A21 tAVLH tAVLL L tLHLL E G DQ0-DQ15 Note: Asynchronous Read CR15 = 1 Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics Symbol t Address Valid to Latch Enable Low ...
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M58LW032C Figure 13. Asynchronous Page Read AC Waveforms A1-A2 A3-A21 DQ0-DQ15 Note: Asynchronous Read CR15 = 1 Table 17. Asynchronous Page Read AC Characteristics Symbol t Address Transition to Output Transition AXQX1 t Address Valid to Output ...
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Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled A1-A21 E L tELWL G tGHWL W DQ0-DQ15 RB V PEN Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled A1-A21 L tELLL E tELWL G tGHWL W DQ0-DQ15 ...
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M58LW032C Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled. Symbol t Address Valid to Latch Enable High AVLH t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High DVWH ...
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Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled A1-A21 W tWLEL G tGHEL E L DQ0-DQ15 RB V PEN Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled A1-A21 L tWLLL W tWLEL G tGHEL E DQ0-DQ15 ...
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M58LW032C Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable Controlled Symbol t Address Valid to Latch Enable High AVLH t Address Valid to Chip Enable High AVEH t Data Input Valid to Chip Enable High DVEH ...
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Figure 18. Synchronous Burst Read AC Waveform Note: Valid Clock Edge = Rising (CR6 = 1) M58LW032C 39/61 ...
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M58LW032C Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output K (2) Output Note: 1. Valid Data Ready = Valid Low during valid clock edge (CR8 = Valid output, NV= Not ...
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Figure 20. Reset, Power-Down and Power-up AC Waveform DQ0-DQ15 tPHQV RB RP tVDHPH VDD, VDDQ Table 21. Reset, Power-Down and Power-up AC Characteristics Symbol t Reset/Power-Down High to Data Valid PHQV t Reset/Power-Down Low to Reset/Power-Down High ...
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M58LW032C PACKAGE MECHANICAL Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 22. TSOP56 - 56 lead Plastic Thin Small Outline ...
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Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Outline BALL "A1" A Note: Drawing is not to scale. Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data Symbol Typ ...
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M58LW032C PART NUMBERING Table 24. Ordering Information Scheme Example: Device Type M58 Architecture L = Page Mode, Burst Operating Voltage 2.7V to 3.6V 1 DDQ Device Function 032C = 32 Mbit ...
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APPENDIX A. BLOCK ADDRESS TABLE Table 25. Block Addresses Block Address Range Number (x16 Bus Width) 32 1F0000h-1FFFFFh 31 1E0000h-1EFFFFh 30 1D0000h-1DFFFFh 29 1C0000h-1CFFFFh 28 1B0000h-1BFFFFh 27 1A0000h-1AFFFFh 26 190000h-19FFFFh 25 180000h-18FFFFh 24 170000h-17FFFFh 23 160000h-16FFFFh 22 150000h-15FFFFh 21 140000h-14FFFFh ...
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M58LW032C APPENDIX B. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine ...
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Table 28. CFI - Device Voltage and Timing Specification Address A21-A1 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and ...
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M58LW032C Table 30. Block Status Register Address A21-A1 (1) (BA+2)h Note specifies the block address location, A21-A17. 2. Not Supported. 48/61 Data 0 Block UnProtected bit0 1 Block Protected 0 Last erase operation ended successfully bit1 1 Last ...
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Table 31. Extended Query information Address Address offset A21-A2 (P)h 31h 50h (P+1)h 32h 52h (P+2)h 33h 49h (P+3)h 34h (P+4)h 35h (P+5)h 36h (P+6)h 37h (P+7)h 38h (P+8)h 39h (P+9)h 3Ah (P+A)h 3Bh (P+B)h 3Ch (P+C)h 3Dh (P+D)h 3Eh ...
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M58LW032C APPENDIX C. FLOW CHARTS Figure 23. Write to Buffer and Program Flowchart and Pseudo Code Note 1: N+1 is number of Words to be programmed Note 2: Next Program Address must have same A5-A21. Note 3: A full Status ...
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Figure 24. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register SR7 = 1 YES SR2 = 1 YES Write FFh Read data from another block Write D0h Program Continues NO NO Program ...
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M58LW032C Figure 25. Erase Flowchart and Pseudo Code Start Write 20h Write D0h to Block Address Read Status Register SR7 = 1 YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES SR1 = 0 YES ...
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Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register SR7 = 1 YES SR6 = 1 YES Write FFh Read data from another block or Program Write D0h Erase Continues NO ...
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M58LW032C Figure 27. Block Protect Flowchart and Pseudo Code Start Write 60h Block Address Write 01h Block Address Read Status Register SR7 = 1 YES SR3 = 1 NO SR4, SR5 = 1,1 NO SR4 = 1 NO Write FFh ...
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Figure 28. Blocks Unprotect Flowchart and Pseudo Code Start Write 60h Write D0h Read Status Register SR7 = 1 YES SR3 = 1 NO SR4, SR5 = 1,1 NO SR5 = 1 NO Write FFh Blocks Unprotect Sucessful NO YES ...
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M58LW032C Figure 29. Protection Register Program Flowchart and Pseudo Code Start Write C0h Write PR Address, PR Data Read Status Register SR7 = 1 YES SR3, SR4 = 1,1 NO SR1, SR4 = 0,1 NO SR1, SR4 = 1,1 NO ...
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Figure 30. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ 98h SIGNATURE YES CFI QUERY B Note 1. The Erase command (20h) can only be issued if the flash is not already ...
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M58LW032C Figure 31. Command Interface and Program Erase Controller Flowchart (b) WAIT FOR COMMAND WRITE READ STATUS READ SIGNATURE CFI QUERY PROGRAM BUFFER LOAD NO PROGRAM D0h COMMAND ERROR YES c 58/61 B READ STATUS READ ARRAY YES NO FFh ...
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Figure 32. Command Interface and Program Erase Controller Flowchart (c). WAIT FOR COMMAND WRITE READ STATUS READ SIGNATURE CFI QUERY READ ARRAY B YES READ STATUS READ ARRAY YES NO FFh NO YES PROGRAM SUSPENDED YES YES 70h NO YES ...
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M58LW032C REVISION HISTORY Table 32. Document Revision History Date Version 11-Mar-2002 -01 First Issue (Data Brief) 10-Jul-2002 -02 Document expanded to full Product Preview Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...