PM30RHC060 STMicroelectronics, PM30RHC060 Datasheet
PM30RHC060
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PM30RHC060 Summary of contents
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Byte/264 Word Page, 1.8V/3V, NAND Flash Memories FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES – Gbit memory array – Mbit spare area – Cost effective solutions for mass storage applications NAND INTERFACE – ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 1. Product List Reference NAND128-A NAND256-A NAND512-A NAND01G-A 2/57 Part Number NAND128R3A NAND128W3A NAND128R4A NAND128W4A NAND256R3A NAND256W3A NAND256R4A NAND256W4A NAND512R3A NAND512W3A NAND512R4A NAND512W4A NAND01GR3A NAND01GW3A NAND01GR4A NAND01GW4A ...
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TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 7. Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SUMMARY DESCRIPTION The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND cell technology referred to as the Small Page family. The de- vices range ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 2. Product Description Reference Part Number Density Width NAND128R3A NAND128W3A NAND128-A 128Mbit NAND128R4A NAND128W4A NAND256R3A NAND256W3A NAND256-A 256Mbit NAND256R4A NAND256W4A NAND512R3A NAND512W3A (1) 512Mbit NAND512-A NAND512R4A NAND512W4A NAND512R3A NAND512W3A NAND512-A 512Mbit NAND512R4A NAND512W4A NAND01GR3A NAND01GW3A ...
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Figure 3. Logic Block Diagram Address Register/Counter Command Interface E Logic WP R Command Register NAND128-A, NAND256-A, NAND512-A, NAND01G-A NAND Flash Memory Array P/E/R Controller, High Voltage Generator Page Buffer Y Decoder I/O Buffers & Latches RB ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 4. TSOP48 and USOP48 Connections, x8 devices NAND Flash (x8 ...
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Figure 6. FBGA55 Connections, x8 devices (Top view through package NAND128-A, NAND256-A, NAND512-A, NAND01G ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 7. FBGA55 Connections, x16 devices (Top view through package 12/ ...
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Figure 8. FBGA63 Connections, x8 devices (Top view through package NAND128-A, NAND256-A, NAND512-A, NAND01G ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 9. FBGA63 Connections, x16 devices (Top view through package I/ 14/57 ...
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MEMORY ARRAY ORGANIZATION The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, 3., Signal Names, for a brief overview of the sig- nals connected to this device. Inputs/Outputs (I/O0-I/O7). Input/Outputs are used to input the selected address, output ...
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BUS OPERATIONS There are six standard bus operations that control the memory. Each of these is described in this section, see Table 5., Bus Operations, for a sum- mary. Command Input Command Input bus operations are used to give commands ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 6. Address Insertion, x8 Devices Bus Cycle I/O7 I/ A16 A15 2 rd A24 A23 3 th( Note set Low or High ...
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COMMAND SET All bus write operations to the device are interpret the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A DEVICE OPERATIONS Pointer Operations As the NAND Flash memories contain two differ- ent areas for x16 devices and three different areas for x8 devices (see Figure 11.) the read command codes (00h, 01h, 50h) are used ...
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Figure 12. Pointer Operations for Programming Address 80h I/O 00h Inputs Areas can be programmed depending on how much data is input. Subsequent 00h commands can be omitted. Address 80h I/O 01h Inputs Areas B, C can ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Operations section. Once the area (main or spare) has been selected using the Read A, Read B ...
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Figure 13. Read (A,B,C) Operations 00h/ I/O 01h/ 50h Command Code Figure 14. Read Block Diagrams Read A Command, X8 Devices Area A (2nd half Page) (1st half Page) A9-A26 (1) A0-A7 Read B ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 15. Sequential Row Read Operations tBLBH1 (Read Busy time) RB 00h/ I/O Address Inputs 01h/ 50h Command Code Figure 16. Sequential Row Read Block Diagrams Read A Command, x8 Devices Area B Area A (2nd ...
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Page Program The Page Program operation is the standard oper- ation to program data to the memory array. The main area of the memory array is pro- grammed by page, however partial page program- ming is allowed where any number ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in an- other page. The Copy Back Program operation does not re- quire external memory ...
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Block Erase Erase operations are done one block at a time. An erase operation sets all of the bits in the ad- dressed block to ‘1’. All previous data in the block is lost. An erase operation consists of three ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Read Status Register The device contains a Status Register which pro- vides information on the current or previous Pro- gram or Erase operation. The various bits in the Status Register convey information and errors on the ...
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Table 11. Status Register Bits Bit Name SR7 Write Protection Program/ Erase/ Read SR6 Controller SR5, SR4, Reserved SR3, SR2, SR1 SR0 Generic Error Read Electronic Signature The device contains a Manufacturer Code and De- vice Code. To read these ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A SOFTWARE ALGORITHMS This section gives information on the software al- gorithms that ST recommends to implement to manage the Bad Blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased ...
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Figure 21. Garbage Collection Valid Page Invalid Page Garbage Collection When a data page needs to be modified faster to write to the first available page, and the previous page is marked as invalid. After several updates it ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Hardware Simulation Models Behavioral simulation models. Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND ...
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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Ta- NAND Flash Min 100,000 10 Ta- not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect de- vice reliability. STMicroelectronics SURE Program and other rel- evant quality documents. Parameter 1.8V devices 3 V devices 1.8V devices 3 V devices Typ Max 200 500 ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- ...
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Table 18. DC Characteristics, 1.8V Devices Symbol Parameter I DD1 Operating I Current DD2 I DD3 Stand-By Current (CMOS) 128Mb, 256Mb, 512Mb devices I DD5 Stand-By Current (CMOS) 512Mb and 1Gb Dual Die devices I Input Leakage Current LI I ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 19. DC Characteristics, 3V Devices Symbol Parameter I DD1 Operating I Current DD2 I DD3 Stand-by Current (TTL), 128Mb, 256Mb, 512Mb devices I DD4 Stand-by Current (TTL) 512Mb and 1Gb Dual Die devices Stand-By Current ...
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Table 20. AC Characteristics for Command, Address, Data Input Alt. Symbol Symbol t Address Latch Low to Write Enable Low ALLWL t ALS t Address Latch High to Write Enable Low ALHWL t Command Latch High to Write Enable Low ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 21. AC Characteristics for Operations Alt. Symbol Symbol t ALLRL1 Address Latch Low Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 Ready/Busy Low ...
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Figure 23. Command Latch AC Waveforms CL tCLHWL (CL Setup time) tELWL (E Setup time tALLWL (ALSetup time) AL I/O Figure 24. Address Latch AC Waveforms CL tELWL (E Setup time) E tWLWH W tALHWL (AL Setup time) ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 25. Data Input Latch AC Waveforms CL E tALLWL (ALSetup time) AL tWLWH W (Data Setup time) I/O Figure 26. Sequential Data Output after Read AC Waveforms E R tRLQV (R Accesstime) I/O tBHRL RB ...
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Figure 27. Read Status Register AC Waveform CL tCLHWL E tELWL W R (Data Setup time) I/O Figure 28. Read Electronic Signature AC Waveform I/O 90h Read Electronic Signature Command Note: Refer to Table 12. ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 29. Page Read A/ Read B Operation AC Waveform CL E tWLWL 00h or Add.N I/O 01h cycle 1 Command Code Note: Address cycle 4 is only required for 512Mb and ...
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Figure 30. Read C Operation, One Page AC Waveform Add. M I/O 50h cycle 1 RB Command Code Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 31. Page Program AC Waveform CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program Setup Code Note: Address cycle 4 is only required for 512Mb and 1Gb ...
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Figure 32. Block Erase AC Waveform CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Setup Command Note: Address cycle 3 is required for 512Mb and 1Gb devices only. Figure 33. Reset ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Ready/Busy Signal Electrical Characteristics Figures 35, 34 and 36 show the electrical charac- teristics for the Ready/Busy signal. The value re- quired for the resistor R can be calculated using P the following equation: V DDmax ...
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PACKAGE MECHANICAL Figure 37. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, Package Outline DIE Note: Drawing is not to scale. Table 22. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 38. USOP48 – lead Plastic Ultra Thin Small Outline,12 x 17mm, Package Outline DIE Note: Drawing not to scale. Table 23. USOP48 – lead Plastic Ultra Thin Small Outline 17mm, ...
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Figure 39. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline FE Note: Drawing is not to scale Table 24. VFBGA55 8 x 10mm - 6x8 ball array, 0.80mm pitch, Package Mechanical Data Symbol Typ A ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 40. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline SE FE Note: Drawing is not to scale Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - ...
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Figure 41. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline FD1 BALL "A1" Note: Drawing is not to scale. Table 26. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data Symbol ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 42. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline FD1 BALL "A1" Note: Drawing is not to scale Table 27. TFBGA63 9x11mm - 6x8 active ball array, ...
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PART NUMBERING Table 28. Ordering Information Scheme Example: Device Type NAND = NAND Flash Memory Density 128 = 128Mb 256 = 256Mb 512 = 512Mb 01G = 1Gb Operating Voltage 1.7 to 1.95V ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A APPENDIX A. HARDWARE INTERFACE EXAMPLES Nand Flash devices can be connected to a micro- controller system bus for code and data storage. For microcontrollers that have an embedded NAND controller the NAND Flash can be connect- ...
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... CL AL NAND Flash NAND Flash W Device RELATED DOCUMENTATION STMicroelectronics has published a set of application notes to support the NAND Flash memories. They are available from the ST Website www.st.com . or from your local ST Distributor. NAND128-A, NAND256-A, NAND512-A, NAND01G-A CLK D flip-flop ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A REVISION HISTORY Table 29. Document Revision History Date Version 06-Jun-2003 1.0 First Issue 07-Aug-2003 2.0 Design Phase 27-Oct-2003 3.0 Engineering Phase Document promoted from Target Specification to Preliminary Data status. V 03-Dec-2003 4.0 Title of for ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...