MAX3945ETE+T Maxim Integrated Products, MAX3945ETE+T Datasheet - Page 16

• Manufacturer Part Number: MAX3945ETE+T
• Description: IC AMP LIMITING 3.3V LP 16TQFN
• Manufacturer: Maxim Integrated Products
• Type: Limiting Amplifierr

Specifications of MAX3945ETE+T

• Applications: Optical Networks
• Mounting Type: Surface Mount
• Package / Case: 16-WQFN Exposed Pad, 16-DQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Table 9. Digital Communication Word Structure
Table 10. Register Descriptions and Addresses
The MAX3945 implements a proprietary 3-wire digital
interface. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL has been set to
1. All data transfers are most significant bit (MSB) first.
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates 16
clock cycles to SCL. All operations transfer 8 bits to the
MAX3945. The RWN bit determines if the cycle is read
or write. See Table 9.
The MAX3945 contains seven registers available for pro-
gramming. Table 10 shows the registers and addresses.
The master generates 16 total clock cycles at SCL. The
master outputs a total of 16 bits (MSB first) to the SDA
16
15
_____________________________________________________________________________________
ADDRESS
3-Wire Digital Communication
14
H0x00
H0x01
H0x02
H0x03
H0x04
H0x0E
H0x12
13
Register Address
12
Write Mode (RWN = 0)
Register Addresses
11
SET_LOSTIMER
MODECTRL
RXCTRL1
RXCTRL2
SET_CML
SET_LOS
RXSTAT
NAME
10
Protocol
General
9
RWN
Receiver Control Register 1
Receiver Control Register 2
Receiver Status Register
CML Output Level Setting Register
LOS Threshold Assert Level Setting Register
General Control Register
LOS Timer Setting Register
8
BIT
line at falling edge of the clock. The master closes the
transmission by setting CSEL to 0. Figure 5 shows the
interface timing, and Table 11 defines the various timing
parameters.
The master generates 16 total clock cycles at SCL. The
master outputs a total of 8 bits (MSB first) to the SDA line
at falling edge of the clock. The SDA line is released after
the RWN bit has been transmitted. The slave outputs 8
bits of data (MSB first) at rising edge of the clock. The
master closes the transmission by setting CSEL to 0.
Figure 5 shows the interface timing.
Normal mode allows read-only instruction for all registers
except MODECTRL. Normal mode is the default mode.
Setup mode allows the master to write unrestricted data
into any register except the RXSTAT register. To enter
setup mode, the MODECTRL register (address = H0x0E)
must be set to H0x12. After the MODECTRL register has
been set to H0x12, the next operation is unrestricted.
The setup mode is automatically exited after the next
operation is finished. This sequence must be repeated if
further unrestricted settings are necessary.
7
6
Data that is written or read.
5
FUNCTION
4
Read Mode (RWN = 1)
3
2
Mode Control
1
0