PALCE22V10Q-25JC/4 Lattice Semiconductor Corp., PALCE22V10Q-25JC/4 Datasheet

PALCE22V10Q-25JC/4

Manufacturer Part Number

PALCE22V10Q-25JC/4

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheets

1.PALCE22V10Q-25JC4.pdf (34 pages)

2.PALCE22V10Q-25JC4.pdf (34 pages)

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

PALCE22V10Q-25JC/4

Manufacturer:

AMD

Quantity:

5 510

Company:

Bonase Electronics (HK) Co., Limited

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PALCE22V10Q-25JC/4

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5 510

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DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and

ﬂip-ﬂops at a reduced chip count.

The PALCE22V10Z is an advanced PAL

erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-

power CMOS SSI/MSI gates and ﬂip-ﬂops at a reduced chip count.

The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby

current, the PALCE22V10Z allows battery-powered operation for an extended period.

The PAL device implements the familiar Boolean logic transfer function, the sum of products. The

PAL device is a programmable AND array driving a ﬁxed OR array. The AND array is programmed

to create custom product terms, while the OR array sums selected terms at the outputs.

The product terms are connected to the ﬁxed OR array with a varied distribution from 8 to16 across

the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each

macrocell can be programmed as registered or combinatorial, and active-high or active low. The

output conﬁguration is determined by two bits controlling two multiplexers in each macrocell.

Publication# 16564

Amendment/0

As fast as 5-ns propagation delay and 142.8 MHz f

Low-power EE CMOS

10 macrocells programmable as registered or combinatorial, and active high or active low to

match application needs

Varied product term distribution allows up to 16 product terms per output for complex

functions

Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)

Global asynchronous reset and synchronous preset for initialization

Power-up reset for initialization and register preload for testability

Extensive third-party software and programmer support

24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC

5-ns and 7.5-ns versions utilize split leadframes for improved performance

Rev: E

Issue Date: November 1998

PALCE22V10 and PALCE22V10Z

Families

24-Pin EE CMOS (Zero Power) Versatile PAL Device

PALCE22V10

PALCE22V10Z

device built with zero-power, high-speed, electrically-

COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25

COM'L: -25

MAX

(external)

IND: -15/25

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