LCK4972 Agere Systems, LCK4972 Datasheet
LCK4972
Related parts for LCK4972
LCK4972 Summary of contents
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... The LCK4972 features a power-on reset function, which automatically resets the device on powerup, providing automatic synchronization between QFB and other outputs. The LCK4972 is 3.3 V/2.5 V compatible and requires no external loop filters. It has the capability of driving 50 transmission lines. Series terminated lines have the ability of driving two 50 fanout ...
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... Figure 4-1. 100 MHz from 50 MHz Example ........................................................................................................................10 Figure 4-2. Pentium Compatible Clocks Example ................................................................................................................10 Figure 4-3. 20 MHz Source Example ...................................................................................................................................10 Figure 4-4. Skew Relative to Qa...........................................................................................................................................10 Figure 4-5. Phase Delay Example Using Two LCK4972s ....................................................................................................11 Figure 4-6. LCK4972 Timing ................................................................................................................................................12 Figure 4-7. Freeze Data Input Protocol ................................................................................................................................13 Figure 4-8. Power Supply Filter ............................................................................................................................................14 Figure 4-9. Dual Transmission Lines....................................................................................................................................15 Figure 4-10 ...
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... REF_SEL TCLK0 0 TCLK1 1 TCLK_Sel Ext_FB fselFB2 MR/OE POWER-ON RESET fsela0:1 fselb0:1 fselc0:1 fselFB0:1 Frz_Clk Frz_Data Inv_Clk Agere Systems Inc. LCK4972 Low-Voltage PLL Clock Driver 0 PHASE 1 VCO DETECTOR LPF SYNC PULSE 2 2 DATA ...
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... LCK4972 Low-Voltage PLL Clock Driver 3 Pin Information 3.1 Pin Diagram MROEB 2 Frz_Clk 3 Frz_Data 4 fselFB2 5 PLL_EN 6 Ref_Sel 7 TCLK_Sel 8 TCLK0 9 TCLK1 10 xtal1 11 xtal2 DDA LCK4972 Figure 3-1. 52-Pin TQFPT Advance Data Sheet March 26, 2004 ...
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... Power DDO 37, 45, 49 19, 20 fselc[1:0] LVTTL * U = Internal pull-up resistors ( Agere Systems Inc. LCK4972 Low-Voltage PLL Clock Driver * I/O — Ground Master Reset and Output Enable Input Outputs disabled (high-impedance state). During this condition the PLL loop is open and the VCO will run at an indeterminate frequency. ...
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... LCK4972 Low-Voltage PLL Clock Driver Table 3-1. Pin Description (continued) Pin Symbol Type 25 QSync LVTTL 26 fselFB1 LVTTL 27 fselFB0 LVTTL 28 V Power DDI 29 QFB LVTTL 31 Ext_FB LVTTL 32, 34, 36, 38 Qb[3:0] LVTTL 40, 41 fselb[1:0] LVTTL 42, 43 fsela[1:0] LVTTL 44, 46, 48, 50 Qa[3:0] LVTTL 52 VCO_Sel LVTTL * U = Internal pull-up resistors ( ...
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... The power-on reset function is designed to reset the system after powerup for synchronization between QFB and other outputs. The LCK4972 has the ability to independently enable/disable each output through a serial input port. When disabled (frozen), the outputs will freeze to the low state while internal state machines remain unaffected. When re-enabled, the outputs initialize synchronously and in phase with those not reactivated ...
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... LCK4972 Low-Voltage PLL Clock Driver 4.1 Device Programming The LCK4972 contains three independent banks of four outputs as well as an independent PLL feedback output. The pos- sible configurations make Agere Systems’ LCK4972 one of the most versatile frequency programming devices. Table 4-4 shows various selection possibilities. ...
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... QFB 1 fselFB2 20 MHz Input Ref Ext_FB VCO = 400 MHz Figure 4-3. 20 MHz Source Example Qc0 Qb3 Qb2 Qb1 Figure 4-4. Skew Relative to Qa LCK4972 Low-Voltage PLL Clock Driver 0 fsela0 LCK4972 4 0 fsela1 Qa 60 MHz (PROCESSOR) 0 fselb0 4 0 fselb1 Qb 60 MHz (PROCESSOR) ...
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... MHz Input Ref Ext_FB Figure 4-5. Phase Delay Example Using Two LCK4972s 4.4 SYNC Output When the output frequencies are not integer multiples of each other, there is a need for a signal for synchronization purpos- es. The SYNC output is designed to address this need. The Qa and Qc banks of outputs are monitored by the device, and a low-going pulse (one period in duration, one period before the coincident rising edges of Qa and Qc) is provided ...
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... March 26, 2004 fVCO Qa Qc Sync Qa Qc Sync Qc( 2) Qa( 6) Sync Qa( 4) Qc( 6) Sync Qc( 2) Qa( 8) Sync Qa( 6) Qc( 8) Sync Qa( 12) Qc( 2) Sync Agere Systems Inc. LCK4972 Low-Voltage PLL Clock Driver 1:1 MODE 2:1 MODE 3:1 MODE 3:2 MODE 4:1 MODE 4:3 MODE 6:1 MODE Figure 4-6. LCK4972 Timing 2333 (F) 11 ...
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... A serial interface was created to eliminate individual output control at the cost of one pin per output. The freeze control logic provides a mechanism for the LCK4972’s clock outputs to be stopped in the logic 0 state. The freeze mechanism allows serial loading of the 12-bit serial input register. This register contains one programmable freeze enable bit for 12 of the 14 output clocks ...
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... Due to its susceptibility to noise with spectral content in this range, a filter for the LCK4972 should be designed to target noise in the 100 kHz to 10 MHz range. The RC filter in provide a broadband filter with approximately 100:1 attenuation for noise with spectral content above 20 kHz. More elaborate power supply schemes may be used to achieve increased power supply noise filtering ...
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... LCK4972 Low-Voltage PLL Clock Driver 4.8 Driving Transmission Lines The output drivers of the LCK4972 were designed for the lowest impedance possible for maximum flexibility. With the LCK4972’s 7 impedance, the drivers can accommodate either parallel or series terminated transmission lines. Point-to-point distribution of signals is the preferred method in today’s high-performance clock networks. Series-terminated or parallel-terminated lines can be used in a point-to-point scheme ...
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... JEDEC four layer board inside a wind is reported at airflows of 200 LFPM and 500 LFPM (linear feet per minute), which JMA is calculated using the following formula: JMA LCK4972 Low-Voltage PLL Clock Driver Min Max –0.3 4.6 –0 ...
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... LCK4972 Low-Voltage PLL Clock Driver - Junction to Case Thermal Resistance JC is the thermal resistance from junction to the top of the case. This number is determined by forcing nearly 100% of the JC heat generated in the die out the top of the package by lowering the top case temperature. This is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit ...
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... Maximum Supply Current Analog V Current DD Input Capacitance Power Dissipation Capacitance 1. The LCK4972 inputs can drive a series of parallel terminated transmission lines on the incident edge. 2. Inputs have pull-up/pull-down resistors, which affect input current MHz, unloaded outputs. Table 6-3. dc Characteristics (T A Parameter ...
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... Maximum PLL Lock Time 1. ac characteristics apply for parallel output termination bypass mode, the LCK4972 divides the input reference clock. 3. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio The crystal frequency range must meet the interface frequency range and the VCO lock range divided by the feedback divider ratio: ...
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... Advance Data Sheet March 26, 2004 7 Outline Diagram 52-pin TQFPT package outline. All dimensions are in millimeters. 12.00 10.00 PIN #1 IDENTIFIER ZONE DETAIL A DETAIL B 0.65 TYP Agere Systems Inc. LCK4972 Low-Voltage PLL Clock Driver 40 39 10.00 12. 1.00 ± 0.05 1.20 MAX SEATING PLANE 0.08 0.05/0.15 1.00 REF 0.25 GAGE PLANE SEATING PLANE ...
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... Ordering Information Table 8-1. LCK4972 Ordering Information Device LCK4972 For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 N. AMERICA: 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & ...