CY7C344B-15PC Cypress Semiconductor Corporation., CY7C344B-15PC Datasheet

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CY7C344B-15PC

Manufacturer Part Number
CY7C344B-15PC
Description
32-macrocell EPLD, 15ns
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C344B-15PC

Case
DIP-28L

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C344B-15PC
Manufacturer:
CYP
Quantity:
865
Cypress Semiconductor Corporation
Document #: 38-03036 Rev. *A
Features
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded ce-
ramic chip carrier (HLCC), the CY7C344B represents the
Selection Guide
MAX is a registered trademark of Altera Corporation.
Maximum Access Time (ns)
Note:
• High-performance, high-density replacement for TTL,
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• Advanced 0.65-micron CMOS EPROM technology to
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
1.
Logic Block Diagram
74HC, and custom logic
increase performance
package
15(22)
15(23)
27(6)
28(7)
Number in () refers to J-leaded packages.
INPUT
INPUT
INPUT
INPUT
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
MACROCELL 24
MACROCELL 26
MACROCELL 28
MACROCELL 30
MACROCELL 32
MACROCELL 2
MACROCELL 4
MACROCELL 6
MACROCELL 8
64 EXPANDER PRODUCT TERM ARRAY
[1]
G
O
B
A
B
U
S
L
L
MACROCELL 11
MACROCELL 13
MACROCELL 15
MACROCELL 17
MACROCELL 19
MACROCELL 21
MACROCELL 23
MACROCELL 25
MACROCELL 27
MACROCELL 29
MACROCELL 31
MACROCELL 1
MACROCELL 3
MACROCELL 5
MACROCELL 7
MACROCELL 9
3901 North First Street
7C344B-15
INPUT
INPUT/CLK 2(9)
INPUT
INPUT
15
32
13(20)
14(21)
1(8)
O
C
O
N
T
R
O
L
I
densest EPLD of this size. Eight dedicated inputs and 16 bidi-
rectional I/O pins communicate to one logic array block. In the
CY7C344B LAB there are 32 macrocells and 64 expander
product terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
The speed and density of the CY7C344B makes it a natural
for all types of applications. With just this one device, the de-
signer can implement complex state machines, registered log-
ic, and combinatorial “glue” logic, without using multiple chips.
This architectural flexibility allows the CY7C344B to replace
multichip TTL solutions, whether they are synchronous, asyn-
chronous, combinatorial, or all three.
C344B–1
32-Macrocell MAX® EPLD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
San Jose
7C344B-20
10(17)
11(18)
12(19)
17(24)
18(25)
19(26)
20(27)
23(2)
24(3)
25(4)
26(5)
3(10)
4(11)
5(12)
6(13)
9(16)
20
INPUT/CLK
Pin Configurations
INPUT
INPUT
INPUT
I/O
I/O
I/O
INPUT/CLK
CA 95134
INPUT
INPUT
INPUT
5
6
7
8
9
10
11
GND
V
Revised December 28, 2002
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CC
12 13 14 1516 1718
4 3 2
Top View
HLCC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CerDIP
1
CY7C344B
7C344B-25
28 27 26
28
27
26
25
24
23
22
21
20
19
18
17
16
15
25
408-943-2600
25
24
23
22
21
20
19
INPUT
INPUT
I/O
I/O
I/O
I/O
V
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
CC
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
C344B–2
C344B–3

Related parts for CY7C344B-15PC

CY7C344B-15PC Summary of contents

Page 1

... All inputs, macrocells, and I/O pins are interconnected within the LAB. The speed and density of the CY7C344B makes it a natural for all types of applications. With just this one device, the de- signer can implement complex state machines, registered log- ic, and combinatorial “ ...

Page 2

... O CC Test Conditions 1.0 MHz 0V 1.0 MHz OUT R1 464 250 (b) C344B–5 1.75V C344B–7 parameter refers to low-level TTL output current. OL CY7C344B [2] ...................– +25 mA [2] .........................................–2.0V to +7.0V [3] Ambient Temperature – +70 C – +85 C Min. Max. 4.75(4.5) 5.25(5.5) 2.4 0.45 2.0 V +0.3 CC – ...

Page 3

... Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C344B contains circuitry to protect device pins from high-static voltages or electric fields; however, normal precautions should be taken to avoid apply- ing any voltage higher than maximum rated voltages ...

Page 4

... RH t LAD SYSTEM CLOCK DELAYt ICS CLOCK DELAY t IC FEEDBACK DELAY t FD Figure 1. CY7C344B Timing Model Over Operating Range Description [5] Com’l/Ind [5] Com’l/Ind Com’l/Ind [5] Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind [6] Com’ ...

Page 5

... Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind CY7C344B 7C344B-15 7C344B-20 7C344B-25 Min. Max. Min. Max. Min. Max ...

Page 6

... CLOCK FROM LOGIC ARRAY t RD DATA FROM LOGIC ARRAY OUTPUT PIN Document #: 38-03036 Rev PD1 PD2 CO1 AS1 CY7C344B C344B-11 C344B- AWH AWL C344B– HIGH IMPEDANCE STATE Page C344B-14 ...

Page 7

... LOGIC ARRAY REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY REGISTER OUTPUT TO ANOTHER LAB Document #: 38-03036 Rev EXP t AWL RSU LATCH FD t PIA CY7C344B LAC LAD t t COMB OD C344B- CLR PRE FD C344B-16 Page ...

Page 8

... Internal Synchronous SYSTEM CL OCK PIN t IN SYSTEM CLOCK AT REGISTER t RSU DATA FROM LOGIC ARRAY Ordering Information Speed (ns) Ordering Code 15 CY7C344B-15HC/HI CY7C344B-15JC/JI CY7C344B-15PC/PI CY7C344B-15WC/WI 20 CY7C344B-20HC/HI CY7C344B-20JC/JI CY7C344B-20PC/PI CY7C344B-20WC/WI 25 CY7C344B-25HC/HI CY7C344B-25JC/JI CY7C344B-25PC/PI Document #: 38-03036 Rev ICS t RH Package Name Package Type ...

Page 9

... Package Diagrams Document #: 38-03036 Rev. *A 28-Pin Windowed Leaded Chip Carrier H64 CY7C344B 51-80077 Page ...

Page 10

... Package Diagrams (continued) Document #: 38-03036 Rev. *A 28-Lead Plastic Leaded Chip Carrier J64 28-Lead (300-Mil) Molded DIP P21 CY7C344B 51-85001-A 51-85014-B Page ...

Page 11

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D-15 Config. A CY7C344B 51-80087 Page ...

Page 12

... Document Title: CY7C344B 32-Macrocell MAX® EPLD Document Number: 38-03036 Issue REV. ECN NO. Date ** 106381 06/15/01 *A 122235 12/28/02 Document #: 38-03036 Rev. *A Orig. of Change SZV Change from Spec #: 38-00860 to 38-03036 RBI Power up requirements added to Operating Range Information CY7C344B Description of Change Page ...

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