IS80C88 Intersil Corporation, IS80C88 Datasheet
IS80C88
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IS80C88 Summary of contents
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... CP80C88 o C IP80C88 o C CS80C88 o C lS80C88 o C CD80C88 o C ID80C88 o C MD80C88 5962-8601601QA o C MR80C88 5962-8601601XA 1 80C88 8MHz PKG. NO. CP80C88-2 E40.6 IP80C88-2 E40.6 CS80C88-2 N44.65 IS80C88-2 N44.65 CD80C88-2 F40.6 ID80C88-2 F40.6 MD80C88-2/B F40.6 - F40.6 MR80C88-2/B J44.A - J44.A FN2949.1 ...
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Pinouts MAX MODE 80C88 MIN MODE 80C88 A10 A10 AD7 AD7 AD6 AD6 AD5 AD5 AD4 AD4 AD3 AD3 AD2 AD2 AD1 AD1 AD0 AD0 80C88 80C88 (DIP) TOP VIEW MIN MODE GND ...
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Functional Diagram EXECUTION UNIT REGISTER FILE DATA POINTER AND INDEX REGS (8 WORDS) 16-BIT ALU FLAGS TEST INTR NMI RQ/GT0 HOLD HLDA CLK MEMORY INTERFACE BUS INTERFACE UNIT EXECUTION UNIT 80C88 BUS INTERFACE UNIT RELOCATION REGISTER FILE SEGMENT ...
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Pin Description The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers). PIN ...
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Pin Description (Continued) The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/ which are unique to the minimum mode are described; all other pin functions are as described above. MINIMUM MODE SYSTEM PIN ...
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Pin Description (Continued) The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to the maximum mode are described; all other pin functions are as described above. ...
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Functional Description Static Operation All 80C88 circuitry is static in design. Internal registers, counters and latches are static and require not refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microproces- sors. The ...
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The BIU will automatically execute two fetch or write cycles for 16-bit operands. Certain locations in memory are reserved for specific CPU operations. (See Figure 2). Locations from addresses FFFF0H through FFFFFH are reserved for operations including a jump to ...
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V CC MN/MX 82C84A/85 CLK IO READY RES WR RESET RDY CLOCK GENERATOR INTA GND 80C88 DT/R CPU DEN ALE 1 GND GND AD0-AD7 C1 ADDR/DATA V CC A8-A19 20 GND ...
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Bus Operation The 80C88 address/data bus is broken into three parts: the lower eight address/data bits (AD0-AD7), the middle eight address bits (A8-A15), and the upper four address bits (A16- A19). The address/data bits and the highest four address bits ...
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TABLE CHARACTERISTICS Interrupt Acknowledge Read I Write I Halt Instruction Fetch Read Data from Memory ...
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Non-Maskable Interrupt (NMI) The processor provides a single non-maskable interrupt (NMI) pin which has higher priority than the maskable interrupt request (INTR) pin. A typical use would be to activate a power failure routine. The NMI is edge-triggered on a ...
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Basic System Timing In minimum mode, the MN/MX pin is strapped to V the processor emits bus control signals (RD, WR, IO/M, etc.) directly. In maximum mode, the MN/MX pin is strapped to GND and the processor emits coded status ...
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The 80C88 and 80C86 are completely software compatible by virtue of their identical execution units. Software that is system dependent may not be completely transferable, but software that is not system dependent will operate equally as well on an 80C88 ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications MINIMUM COMPLEXITY SYSTEM SYMBOL PARAMETER TIMING REQUIREMENTS (1) TCLCL CLK Cycle Period (2) TCLCH CLK Low Time (3) TCHCL CLK High Time (4) TCH1CH2 CLK Rise Time (5) TCL2CL1 ...
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AC Electrical Specifications MINIMUM COMPLEXITY SYSTEM SYMBOL PARAMETER (25) TLLAX Address Hold Time to ALE Inactive (26) TCLDV Data Valid Delay (27) TCLDX2 Data Hold Time (28) TWHDX Data Hold Time After ...
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Waveforms CLK (82C84A OUTPUT) (30) TCHCTV IO/M, SSO A15-A8 (17) TCLAV A19/S6-A16/S3 (23) TCLLH ALE RDY (82C84A INPUT) SEE NOTE 9, 10 READY (80C88 INPUT) AD7-AD0 RD READ CYCLE (WR, INTA = DT/R DEN FIGURE 22. BUS ...
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Waveforms (Continued) CLK (82C84A OUTPUT) (17) TCLAV AD7-AD0 DEN WRITE CYCLE WR (19) TCLAZ AD7-AD0 DT/R INTA CYCLE (NOTE 11) RD INTA DEN SOFTWARE HALT - AD7-AD0 DEN, RD, WR, INTA = V TCLAV OH (17) ...
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AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) SYMBOL PARAMETER TIMING REQUIREMENTS (1) TCLCL CLK Cycle Period (2) TCLCH CLK Low Time (3) TCHCL CLK High Time (4) TCH1CH2 CLK ...
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AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) SYMBOL PARAMETER (32) TCLMCL MCE Inactive Delay (Note 13) (33) TCLDV Data Valid Delay (34) TCLDX2 Data Hold Time (35) TCVNV Control ...
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Waveforms CLK TCLAV QS0, QS1 (21) TCHSV S2, S1, S0 (EXCEPT HALT) A15-A8 (23) TCLAV A19/S6-A16/S3 TSVLH (27) TCLLH ALE (82C88 OUTPUT) NOTES 18, 19 RDY (82C84 INPUT) READY 80C86 INPUT) READ CYCLE TCLAV AD7-AD0 RD (41) TCHDTL DT/R 82C88 ...
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Waveforms (Continued) CLK TCHSV (21) S2, S1, S0 (EXCEPT HALT) WRITE CYCLE AD7-AD0 DEN 82C88 OUTPUTS AMWC OR AIOWC SEE NOTES 22, 23 MWTC OR IOWC INTA CYCLE A15-A8 (SEE NOTES 25, 26) (25) TCLAZ AD7-AD0 (28) TSVMCH MCE/PDEN (30) ...
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Waveforms (Continued) CLK TCLGH (44) (1) TCLCL RQ/GT PREVIOUS GRANT AD7-AD0 RD, LOCK A19/S6-A16/S3 S2, S1, S0 FIGURE 26. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) NOTE: The coprocessor may not drive the busses outside the region shown without risking contention. ...
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Waveforms (Continued) AC Test Circuit OUTPUT FROM DEVICE UNDER TEST CL (NOTE) NOTE: Includes stay and jig capacitance. Burn-In Circuits GND RIO GND RIO VCL RIO GND RIO GND RIO VCL RIO GND RIO GND RIO GND RIO VCL RIO ...
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Burn-In Circuits (Continued) RIO RIO RIO RIO RIO RIO RIO GND NOTES: = 5.5V ±0.5V, GND = 0V Input voltage limits (except clock): V (Maximum (Minimum) = 2.6V, V (Clock ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...
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Instruction Set Summary MNEMONIC AND DESCRIPTION DATA TRANSFER MOV = MOVE: Register/Memory to/from Register Immediate to Register/Memory Immediate to Register Memory to Accumulator Accumulator to Memory Register/Memory to Segment Register †† Segment Register to Register/Memory PUSH = Push: Register/Memory Register ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Immediate to Register/Memory Immediate to Accumulator INC = Increment: Register/Memory Register AAA = ASCll Adjust for Add DAA = Decimal Adjust for Add SUB = Subtract: Register/Memory and Register to Either Immediate from ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION RCR = Rotate Through Carry Right AND = And: Reg./Memory and Register to Either Immediate to Register/Memory Immediate to Accumulator TEST = And Function to Flags, No Result: Register/Memory and Register Immediate Data ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Intersegment Intersegment Adding Immediate to SP JE/JZ = Jump on Equal/Zero JL/JNGE = Jump on Less/Not Greater or Equal JLE/JNG = Jump on Less or Equal/ Not Greater JB/JNAE = Jump on Below/Not ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...