MT48LC8M32B2P-7 Micron Semiconductor Products, MT48LC8M32B2P-7 Datasheet

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SYNCHRONOUS DRAM Features • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst ...

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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 1: Pin Assignment (Top View) 86-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Figure 2: 90-Ball FBGA Assignment (Top View DQ26 B DQ28 CLK K DQM1 ...

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... SDRAM Part Number PART NUMBER ARCHITECTURE MT48LC8M32B2TG 8 Meg x 32 MT48LC8M32B2P 8 Meg x 32 MT48LC8M32B2F5 8 Meg x 32 MT48LC8M32B2B5 8 Meg x 32 General Description The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK) ...

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Figure 3: Functional Block Diagram – 8 Meg x 32 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 09005aef8140ad6d MT48LC8M32B2_2.fm - Rev. B 10/04 EN BANK 0 ...

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Table 2: Pin Descriptions (TSOP) 86-PIN TSOP SYMBOL 68 CLK 67 CKE 20 CS# 17, 18, 19 WE#, CAS#, RAS# 16, 71, 28, 59 DQM0− DQM3 22, 23 BA0, BA1 25-27, 60-66, 24, A0–A11 ...

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Table 3: Ball Descriptions (FBGA) 90-BALL FBGA SYMBOL J1 CLK J2 CKE J8 CS# J9, K7, K8 RAS#, CAS#, WE# K9, K1, F8, F2 DQM0-3 J7, H8 BA0, BA1 G8, G9, F7, F3, G1, A0–A11 G2, G3, H1, H2, J3, ...

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Functional Description In general, this 256Mb SDRAM (2 Meg banks quad-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). ...

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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by ...

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CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availabil- ity of the first piece of output data. The latency can be set to one, two, or three clocks. ...

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Commands Table 6 provides a quick reference of available com- mands. This is followed by a written description of each command. Three additional Truth Tables (Tables Table 6: Truth Table 1 – Commands and DQM Operation Note 1 NAME (FUNCTION) ...

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READ The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0–A8 selects the starting column location. ...

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Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM pro- vides its own internal clocking, causing ...

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READs READ bursts are initiated with a READ command, as shown in Figure 8. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto ...

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CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. 09005aef8140ad6d MT48LC8M32B2_2.fm - Rev. B 10/04 EN Figure 10: Consecutive READ Bursts ...

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COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS NOTE: Each READ command may be to either bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed- length READ burst may ...

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Figure 12: READ-to-WRITE CLK DQM COMMAND READ NOP NOP BANK, ADDRESS COL n DQ NOTE used for illustration. The READ command may be to any bank, and the WRITE command may be to ...

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Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMI- NATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles ...

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Figure 15: Terminating a READ Burst CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: DQM is LOW. WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 16 on page 22. The ...

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WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies ...

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Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed- length WRITE burst may be immediately followed by a READ command. Once the READ command is regis- tered, the data inputs will ...

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Figure 21: WRITE to PRECHARGE CLK CLK ( CK > WR) DQM COMMAND WRITE NOP NOP PRECHARGE BANK BANK a, ADDRESS (a or all) COL ...

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Figure 24: Power-Down ( ( ) ) CLK ( ( ) ) t CKS CKE ( ( ) ) ( ( ) ) COMMAND NOP ( ( ) ) All banks idle Input buffers gated off Enter power-down mode Exit ...

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Figure 27: READ With Auto Precharge Interrupted by a READ COMMAND Internal States BANK m ADDRESS NOTE: DQM is LOW. Figure 28: READ With Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS NOTE: DQM ...

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Figure 29: WRITE With Auto Precharge Interrupted by a READ CLK COMMAND BANK n Internal States BANK m ADDRESS DQ NOTE: DQM is LOW. Figure 30: WRITE With Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK ...

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Table 7: Truth Table 2 – CKE Notes 1–4 CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing ...

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Table 8: Truth Table 3 – Current State Bank n, Command To Bank n Notes 1–11; notes appear below and on next page CURRENT STATE CS# RAS# CAS# WE Any L H Idle ...

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The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when ...

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Table 9: Truth Table 4 – Current State Bank n, Command To Bank m Notes 1–17; notes appear below and on next page CURRENT STATE CS# RAS# CAS# WE Any L H Idle X X Row Activating, L ...

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READs or WRITEs to bank m listed under Command (Action) include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when ...

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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...

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Table 12: Electrical Characteristics and Recommended AC Operating Conditions Notes appear on page 37 PARAMETER Access time from CLK (positive edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE ...

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Table 13: AC Functional Characteristics Notes appear on page 37 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to ...

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Table 14: I Specifications and Conditions DD Notes appear on page PARAMETER/CONDITION Operating Current: Active Mode; Burst = 2; READ or WRITE (MIN Standby Current: Power-Down ...

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Notes 1. All voltages referenced This parameter is sampled MHz 25°C; pin under test biased at 1.4V can range from 0pF to 6pF dependent on output loading ...

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Figure 31: Initialize and Load Mode Register CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ( ) ...

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CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP DQM 0–3 A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all ...

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CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM0– A0–A9, A11 COLUMN ...

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T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0–3 A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks 09005aef8140ad6d MT48LC8M32B2_2.fm - ...

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T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0–3 A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks 09005aef8140ad6d MT48LC8M32B2_2.fm - ...

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Figure 36: Single Read – Without Auto Precharge T0 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 t AS ...

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Figure 37: Read – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 ROW A0–A9, A11 ROW A10 DISABLE ...

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Figure 38: Read – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0– A0–A9, A11 ROW ENABLE ...

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Figure 39: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0– ROW A0–A9, A11 ENABLE AUTO PRECHARGE ROW ...

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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0– A0–A9, A11 COLUMN m 2 ROW ROW ...

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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0– A0–A9, A11 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE t AS ...

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T0 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 BA0, BA1 BANK DQ t RCD ...

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Figure 43: Write – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0– A0–A9, A11 ROW ROW A10 DISABLE ...

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Figure 44: Write – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0– A0–A9, A11 COLUMN m 3 ROW ...

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Figure 45: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0– COLUMN m 3 ROW A0–A9, A11 t ...

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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0– A0–A9, A11 ROW ROW A10 BA0, BA1 BANK DQ ...

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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0– A0–A9, A11 ROW ROW A10 BA0, BA1 BANK DQ ...

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TYP 0. 0.75 PIN # 1.00 PLATED LEAD FINISH: 90% Sn, 10% Pb (TG) OR 100% Sn (P) PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ...

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Figure 49: 90-Ball FBGA (8mm x 13mm) 0.65 ±0.05 SEATING PLANE C 0.10 C 90X Ø0.45 ±0.05 6.40 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø0.42 BALL A9 11.20 ±0.10 5.60 ±0.05 3.20 ±0.05 ...