DSP56ADC16S Motorola, DSP56ADC16S Datasheet
DSP56ADC16S
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DSP56ADC16S Summary of contents
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... No-glue Interface to DSP5600x/DSP561xx and Most Other General Purpose DSPs • This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA INC., 1992 32 KHz to 400 KHz (Comb Filter) Order this data sheet by DSP56ADC16/D ...
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... Input End Frame Sync Input Clock Input (12.8 MHz) MOTOROLA 2 pled signal is lowpass filtered, effectively removing the out-of-band quantization noise. The lowpass filtering is then followed by decimation to reduce the output sam- ple rate commensurate with the frequency band of in- terest and to increase the resolution. In the DSP56ADC16, the filtering and decimation are done in two steps to reduce digital filter complexity ...
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... FSI allows multiple DSP56ADC16’ synchronized using a common frame sync source. A DSP56ADC16 common CLKIN signal is required when using a com- mon frame sync signal with multiple DSP56ADC16s. Analog + Input (V This pin is the A/D converter analog non-inverting in- put input anti-aliasing filter is used prior to the ...
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... This pin is NOT internally connected to dig- ital ground (DGND). Digital Ground (DGND) This pin is the ground connection for digital internal circuitry and pin drivers. MOTOROLA 4 Filter Select (FSEL) This input allows selection of the FIR filter output or the comb filter output. When FSEL is low, the SDO pin will deliver the final lowpass/compensation FIR filter output ...
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... It is important to note 16 THREE-STATE DRIVER 16-BIT SHIFT REGISTER FILTER SELECT Figure 3. Block Diagram of Serial Interface 4 sin ----- - ---------------------------- - sin --- - f s SERIAL CLOCK OUT SERIAL DATA OUT FRAME SYNC OUT DATA OUTPUT ENABLE MOTOROLA 5 ...
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... A/D converter imple- mentation: successive approximation (SA), integrat- ing, and flash. They are implemented using the Nyquist sampled data criterion (set a minimum of MOTOROLA 6 Figure 6. Magnitude Response of FIR Filter twice the signal frequency) instead of the oversam- pled method used by the sigma-delta technology. ...
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... In contrast, sigma-delta modulation based A/D tech- nology can meet the performance goals of 16-bit res- olution and 100 KHz sample rate with moderate cost. A tutorial of sigma-delta technology can be found in the Motorola Digital Signal Processing Operation Ap- plication Report, APR8/D, entitled “Principles of Sig- ma-Delta +5V C1 ...
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... Converters” which can be requested from: Motorola Literature Distribution P.O. Box 20912 Phoenix, Arizona 85036 or from the other Motorola literature distribution cen- ters listed on the back cover of this data sheet. PERFORMANCE EVALUATIONS Figure 7 shows the input circuitry used for testing sig- nal-to-noise and signal-to-THD ratios. A low distortion (> ...
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... Figure 13. Typical Measured Group Delay of Comb Filter Output Figure 14. Typical Measured Group Delay of FIR Filter Output DSP56ADC16 Settling Time 17.0 s 13.5 s (Average of 50 sweeps) Group Delay Settling Time 340 s 680 s 13.5 s (No Sweeping Average) 340 s Input Sinewave Frequency: 20.0 KHz CLKIN Freuency: 12.8 MHz Input Sinewave Frequency: 1.0 KHz CLKIN Freuency: 12.8 MHz MOTOROLA 9 ...
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... Analog Ground Digital Ground MOTOROLA 10 synchronized, this results in the multiplex intervals of mux (output sample interval). If the FSI and the multiplexer are not synchronized, there can be one sample of time uncertainty so that 12.8 MHz, the minimum multiplex intervals, clk ...
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... K 330 68 pF 74HCU04 68 pF Figure 16. Schematic Diagram for Multiplexing Two DSP56ADC16s with the DSP56001 DSP56ADC16 better performance, the recommended conversion circuit diagram from single-ended input to differential input is illustrated in Figure 18. Using this diagram, the analog input voltage range can be conditioned to utilize DSP56ADC16 ...
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... LOGIC 0 DSP56ADC16 FS0 SD0 SC0 SFMT DOE LOGIC 0 Figure 17. Connection Diagram Examples Figure 18. Single Ended to Differential Analog Input Diagram MOTOROLA 12 DSP56ADC16 DSP5600x PC5/FSR PC7/SRD PC6/SCK DSP56ADC16 ADSP21xx RFS1 DR1 SCLK1 DSP56ADC16 TMS320Cxx FSR DR CLKR 10 K 100 – ...
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... SCO cycles as shown in Figure 19. A single FSI pulse from the octal counter (74ASL867) is used for both DSP56ADC16s to make sure that the FSIs for both chips are occurring at the same time. The out- puts of the first DSP56ADC16 and the 16-bit shift reg- ister can be combined by one OR gate to yield one serial output to the SSI port ...
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... Figure 19. Synchronized Two Channel Input Sampling for Stereo Applications FSO SDO 1 SC0 • Memory mapped structure for each channel • Can be expanded to N channels Figure 20. Block Diagram for Synchronized Sampling of more than Two Analog Channels MOTOROLA 14 channel 1 DSP56ADC16 SC0 FSI FS0 SD0 ...
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... Electrical Specifications Symbol Vcc stg = 2.0V V REF pp Symbol JA JC Power Considerations , in C can be obtained from: J and can be neglected. An appropriate relationship between P INT = 0 Vdc) SS Value Unit -0.3 to +7.0 Vcc - 0 0 -40 to +85 -55 to +150 3.5 Value Rating 68 C/W 0.7 C/W MOTOROLA (1) and (2) 15 ...
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... JC junction temperature. Values for thermal resistance presented in this document, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for MC68XX Microcomponent Devices”, and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup. User-derived values for thermal resistance may differ ...
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... I 1 TSI 300 400 D Z Note Note 2 ref 2.5V ref Min Typ Max (Note 2) 50 0.3 3.0 Vcc Vcc Vcc - 4% 0.4* 0. Unit Unit Bits dB dB LSBs ppm MOTOROLA 17 ...
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... Frame Sync Output Setup Time before Falling Edge of SCO 19 Frame Sync Output Hold Time after Falling Edge of SCO 20 Serial Data Output Setup Time 21 Serial Data Output Hold Time 22 Delay from Frame Sync Input to Frame Sync Output 23 Serial Clock Output Period MOTOROLA 18 Characteristic Symbol sdosu ...
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... FSI must be deasserted for at least two CLKIN periods prior to being asserted. Figure 21. Timing Diagram for CLKIN/FSI/SCO When FSEL=0 DSP56ADC16 Vcc ( =5V 10%, T =50 pF+1 TTL load FIR Filter Output Mode o =- Symbol Min Max Unit doedv ‡ doedz 2 MOTOROLA ...
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... SCO 9 FSO SDO Zero (After previous D0) SCO FSO 16 SDO Zero (After previous D0) *The FSI input must be deasserted for at least two CLKIN periods prior to being asserted. Figure 22. Timing Diagram for FSO/SCO/SDO When FSEL=0 MOTOROLA D15 D14 D13 13 Low for D15-D0 11 ...
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... Valid for first 16 SCO cycles 32 SCO cycles Low (asserted) for first 16 SCO cycles Valid for first 16 SCO cycles FIR Filter Output Mode Zero for last 16 SCO cycles VALID High (deasserted) for last 16 SCO cycles VALID Zero for last 16 SCO Cycles MOTOROLA 21 ...
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... FSO 20 SDO D1 *The FSI must be deasserted for at least two CLKIN periods prior to being asserted. Figure 24. Timing Diagrams for FSO/SCO/SDO When FSEL=1 DOE Data Out Figure 25. Timing Diagrams of DOE and Data Output MOTOROLA SCO Cycles D15 D14 D13 COMB Filter Output Mode ...
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... DSP56ADC16 SPECIFICATION DEFINITIONS is the frequency at which the device response is within the ripple is the frequency at which the device response below the pass- is the frequency at which the device response above the current is sourced from that refin MOTOROLA 23 ...
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... Input Analog Voltage Range are produced which properly represent the input voltage signal. MOTOROLA 24 is when one of the two analog inputs is held at a fixed voltage level and the is the range of input voltage over which meaningful digital output codes ...
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... DSP56ADC16 Electrical Characteristics Ordering Information Order this part by the part number: DSP56ADC16S DSP56ADC16 Package Dimensions MOTOROLA 25 ...
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifi ...
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... SNR and THD test conditions kHz Differential Sinewave; CLKIN = 6.4 MHz; FIR word-wide Mode; Using Internal V This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA INC., 1992 ”, should read “ns”. clk ...