PM7349-BI PMC-Sierra Inc, PM7349-BI Datasheet
PM7349-BI
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PM7349-BI Summary of contents
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... Quad J2, E3 and DS-3 Framer Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000314, Issue 5 PM7349 S/UNI- TM 4xD3F S/UNI-4xD3F Data Sheet Released Issue 5: June 2001 S/UNI®-4xD3F Data Sheet Released ...
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Legal Information Copyright © 2001 PMC-Sierra, Inc. The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written ...
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Contacting PMC-Sierra PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal ...
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Revision History Issue No. Issue Date 5 June 2001 4 July 2000 3 July 2000 2 June 2000 1 March 2000 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000314, Issue 5 Details of ...
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Table of Contents 1 Features.....................................................................................................................14 2 Applications ...............................................................................................................16 3 References ................................................................................................................17 4 Definitions ..................................................................................................................19 5 Application Example ..................................................................................................21 6 Block Diagram ...........................................................................................................22 7 Description.................................................................................................................23 8 Pin Diagram ...............................................................................................................26 9 Pin Descriptions.........................................................................................................28 10 Functional Description ...............................................................................................40 10.1 DS3 Framer.......................................................................................................40 10.2 E3 ...
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G.832 E3 Frame Format .................................................................................182 13.6 J2 Frame Format ............................................................................................183 13.7 Servicing Interrupts .........................................................................................184 13.8 Using the Performance Monitoring Features ..................................................185 13.9 Using the TDPR Internal PMDL Transmitter ...................................................185 13.9.1 TDPR Polling Mode............................................................................186 13.9.2 TDPR Interrupt-driven Mode ..............................................................187 13.9.3 ...
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List of Registers Register 000H, 100H, 200H, 300H: S/UNI-4xD3F Configuration .....................................58 Register 001H, 101H, 201H, 301H: S/UNI-4xD3F Configuration 2 ..................................60 Register 002H, 102H, 202H, 302H: S/UNI-4xD3F Transmit Configuration.......................62 Register 003H, 103H, 203H, 303H: S/UNI-4xD3F Receive Configuration .......................64 Register 004H, 104H, ...
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Register 03AH, 13AH, 23AH, 33AH: E3 FRMR Framing Interrupt Enable .......................99 Register 03BH, 13BH, 23BH, 33BH: E3 FRMR Framing Interrupt Indication and Status......................................................................................................................100 Register 03CH, 13CH, 23CH, 33CH: E3 FRMR Maintenance Event Interrupt Enable ....................................................................................................................102 Register 03DH, 13DH, 23DH, 33DH: ...
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Register 092H, 192H, 292H, 392H: TTB Indirect Address..............................................148 Register 093H, 193H, 293H, 393H: TTB Indirect Data ...................................................149 Register 094H, 194H, 294H, 394H: TTB EXPLD Type Label .........................................150 Register 095H, 195H, 295H, 395H: TTB Payload Type Label Control/Status ................151 Register 098H, ...
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List of Figures Figure 1 S/UNI-4xD3F Operating as a Quad Framer Device in Frame Relay Equipment .......................................................................................................21 Figure 2 Block Diagram ...................................................................................................22 Figure 3 Framing Algorithm (CRC_REFR = 0)................................................................46 Figure 4 Framing Algorithm (CRC_REFR = 1)................................................................47 Figure 5 DS3 Frame ...
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Figure 34 Transmit Unipolar DS3 Stream .....................................................................209 Figure 35 Transmit Bipolar E3 Stream ..........................................................................209 Figure 36 Transmit Unipolar E3 Stream........................................................................210 Figure 37 Transmit Bipolar J2 Stream ..........................................................................210 Figure 38 Transmit Unipolar J2 Stream ........................................................................211 Figure 39 Generic Transmit Stream ..............................................................................211 ...
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List of Tables Table 1 Transmission System Sublayer Processing Acceptance and Output ................23 Table 2 Summary of Receive and Detection Features ...................................................23 Table 3 J2 Framer Multiframe Format.............................................................................44 Table 4 Register Memory Map ........................................................................................54 Table 5 STATSEL[2:0] Options .......................................................................................61 Table ...
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Table 34 Microprocessor Interface Write Access (Figure 65) .......................................226 Table 35 RSTB Timing (Figure 62) ...............................................................................228 Table 36 Transmit Interface Timing (Figure 63)............................................................228 Table 37 Receive Interface Timing (Figure 64).............................................................233 Table 38 JTAG Port Interface (Refer to Figure 65) .......................................................235 ...
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Features The S/UNI®–4xD3F is a quad DS3, E3 (G.751 and G.832), and J2 framer device. Each channel can be independently configured as a DS3, E3 Framer. Furthermore, it: • Optionally generates gapped transmit and receive clocks for ...
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The transmitter section: • Provides frame insertion for the M23 or C-bit parity DS3 applications, alarm insertion, and diagnostic features. Also inserts, FEAC codes and provides an integral HDLC transmitter to insert the PMDL. • Provides frame insertion for the ...
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Applications • SONET/SDH Mux E3/DS3 Tributary Interfaces • PDH Mux J2/E3/DS3 Line Interfaces • DS3/E3/J2 Digital Cross Connect Interfaces • DS3/E3/J2 PPP Internet Access Interfaces • DS3/E3/J2 Frame Relay Interfaces Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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References • ANSI T1.627 - 1993, “Broadband ISDN - ATM Layer Functionality and Specification”. • ANSI T1.107a - 1990, “Digital Hierarchy - Supplement to Formats Specifications (DS3 Format Applications)”. • ANSI T1.107 - 1995, “Digital Hierarchy - Formats Specifications”. ...
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ETS 300 687, “Business TeleCommunications (BTC); 34 Mbit/s digital leased lines (D34U and D34S); Connection characteristics”, January 1996. • Telcordia, GR-499-CORE, “Transport Systems Generic Requirements (TSGR): Common Requirements”, Issue 1, Dec. 1995. • ANSI T1.624 - 1993, “Broadband ISDN ...
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Definitions The following table defines the abbreviations used in this document. AIC Application Identification Channel AIS Alarm Indication Signal ATM Asynchronous Transfer Mode BIP Bit Interleaved Parity CMOS Complementary Metal Oxide Semiconductor COFA Change of Frame Alignment CPERR Path ...
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RBOC Bit Oriented Code Detector RDLC Data Link Receiver RED Receive Error Detection SBGA Super Ball Grid Array TM SATURN® Compatible Interface Specification for PHY and ATM SCI-PHY layer devices SMDS Switched Multi-Megabit Data Service SONET Synchronous Optical Network TAP ...
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... Application Example The PM7349 S/UNI-4xD3F is functionally equivalent to a PM7349 S/UNI-QJET placed in DS3/E3/J2 Transceiver mode J2/E3/T3 framer, the S/UNI-4xD3F can be used in router, frame relay switch, and multiplexer applications. Refer to Figure 1. Figure 1 S/UNI-4xD3F Operating as a Quad Framer Device in Frame Relay Equipment Access Side ...
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Block Diagram Figure 2 Block Diagram TPOS/TDATO[4:1] TNEG/TOHM[4:1] RCLK[4:1] RPOS/RDATI[4:1] RNEG/RLCV/ROHM[4:1] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000314, Issue 5 XBOC TDPR Tx 1/2 TTB Tx Tx O/H Tx Trail FEAC ...
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... Description The PM7349 S/UNI-4xD3F is comprised of integrated quad DS3, E3, and J2 framers functionally equivalent to a PM7346 S/UNI-QJET placed in DS3/E3/J2 Transceiver mode. The S/UNI-4xD3F contains: • Integral DS3 framers that provide DS3 framing and error accumulation in accordance with ANSI T1.107, and T1.107a. • ...
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In the E3 receive direction, the S/UNI-4xD3F frames to G.751 and G.832 E3 signals with a maximum average reframe times of 135 µs for G.751 frames and 250 µs for G.832 frames. LCVs, LOS, framing bit errors, alarm indication signals ...
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The S/UNI-4xD3F requires a software. initialization sequence in order to guarantee proper device operation and long term reliability. Please refer to Section 13.1 of this document for the details on how to program this sequence. Proprietary and Confidential to PMC-Sierra, ...
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Pin Diagram The S/UNI-4xD3F is packaged in a 256-pin SBGA package having a body size and a pin pitch of 1.27 mm. Quadrant A11/A20 to K11/K20 VSS VSS VSS ...
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Quadrant L11/L20 to Y11/Y20 VSS VSS VSS VSS NC VSS P VSS VSS VSS R VSS VSS VSS VDD VDD W ...
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Pin Descriptions Pin Name Type TPOS[4] Output TPOS[3] TPOS[2] TPOS[1] TDATO[4] TDATO[3] TDATO[2] TDATO[1] TNEG[4] Output TNEG[3] TNEG[2] TNEG[1] TOHM[4] TOHM[3] TOHM[2] TOHM[1] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000314, Issue ...
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Pin Name Type Output TCLK[4] TCLK[3] TCLK[2] TCLK[1] RPOS[4] Input RPOS[3] RPOS[2] RPOS[1] RDATI[4] RDATI[3] RDATI[2] RDATI[1] RNEG[4] Input RNEG[3] RNEG[2] RNEG[1] RLCV[4] RLCV[3] RLCV[2] RLCV[1] ROHM[4] ROHM[3] ROHM[2] ROHM[1] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ ...
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Pin Name Type Input RCLK[4] RCLK[3] RCLK[2] RCLK[1] TOHINS[4] Input TOHINS[3] TOHINS[2] TOHINS[1] TOH[4] Input TOH[3] TOH[2] TOH[1] TOHFP[4] Output TOHFP[3] TOHFP[2] TOHFP[1] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000314, Issue 5 ...
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Pin Name Type Output TOHCLK[4] TOHCLK[3] TOHCLK[2] TOHCLK[1] REF8KI Input TDATI[4] TDATI[3] TDATI[2] TDATI[1] TFPO[4] Output TFPO[3] TFPO[2] TFPO[1] TMFPO[4] TMFPO[3] TMFPO[2] TMFPO[1] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000314, Issue 5 ...
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Pin Name Type Output TGAPCLK[4] TGAPCLK[3] TGAPCLK[2] TGAPCLK[1] TFPI[4] Input TFPI[3] TFPI[2] TFPI[1] TMFPI[4] TMFPI[3] TMFPI[2] TMFPI[1] TICLK[4] Input TICLK[3] TICLK[2] TICLK[1] ROHFP[4] Output ROHFP[3] ROHFP[2] ROHFP[1] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ...
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Pin Name Type Output ROH[4] ROH[3] ROH[2] ROH[1] ROHCLK[4] Output ROHCLK[3] ROHCLK[2] ROHCLK[1] REF8KO[4] Output REF8KO[3] REF8KO[2] REF8KO[1] RFPO[4] RFPO[3] RFPO[2] RFPO[1] RMFPO[4] RMFPO[3] RMFPO[2] RMFPO[1] ROVRHD[4] Output ROVRHD[3] ROVRHD[2] ROVRHD[1] Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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Pin Name Type Output RSCLK[4] RSCLK[3] RSCLK[2] RSCLK[1] RGAPCLK[4] RGAPCLK[3] RGAPCLK[2] RGAPCLK[1] RDATO[4] RDATO[3] RDATO[2] RDATO[1] FRMSTAT[4] Output FRMSTAT[3] FRMSTAT[2] FRMSTAT[1] CSB Input WRB Input RDB Input I/O D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Proprietary and Confidential to ...
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Pin Name Type Input A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB Input ALE Input INTB Output TCK Input TMS Input TDI Input TDO Output TRSTB Input BIAS Input Proprietary and Confidential to PMC-Sierra, Inc., and ...
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Pin Name Type Power VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] VDD[9] VDD[10] VDD[11] VDD[12] VDD[13] VDD[14] VDD[15] VDD[16] VDD[17] VDD[18] VDD[19] VDD[20] VDD[21] VDD[22] VDD[23] VDD[24] VDD[25] VDD[26] VDD[27] VDD[28] Proprietary and Confidential to PMC-Sierra, Inc., and for ...
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Pin Name Type Ground VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[35] ...
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Pin Name Type Ground VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71 connect Notes 1. All S/UNI-4xD3F inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels. ...
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All S/UNI-4xD3F outputs and bi-directionals have at least 3 mA drive capability. The data bus outputs, D[7:0], have 3 mA drive capability. The outputs TCLK[4:1], TPOS [4:1], TNEG [4:1], TFPO/TMFPO/TGAPCLK[4:1], RDATO[4:1], ROVRHD[4:1], RSCLK/RGAPCLK[4:1], and REF8KO/ RFPO/RMFPO[4:1] have 6 mA ...
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Functional Description The S/UNI 4xD3F devices contains the following blocks: • Framers for DS3, E3, and J2 • RBOC Bit-oriented code detector • RDLC PMDL receiver • PMON Performance monitor accumulator • PRGD Pseudo-random sequence generator/detector • Transmitters for ...
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Also while in-frame, LCVs, M-bit or F-bit framing bit errors, and P-bit parity errors are indicated. When C-bit parity mode is enabled, both C-bit parity errors and FEBEs are indicated. These error indications, as well as the LCV and excessive ...
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The T3-FRMR can be enabled to automatically assert the RAI, the outgoing transmit stream upon detection of any combination of LOS, OOF or RED, or AIS. The T3-FRMR can also be enabled to automatically insert C-bit Parity FEBE upon detection ...
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The General Purpose Communication Channel byte and presents it to the RDLC when the RNETOP bit in the S/UNI-4xD3F Data Link and FERF Control register is logic zero. The byte is also brought out on the ROH[x] output with ...
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J2 Framer The J2-FRMR integrates circuitry to decode a unipolar or B8ZS encoded signal and frame to the resulting 6312 kbps J2 bit stream. Having found frame, the J2-FRMR extracts a variety of overhead and datalink information from the ...
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J2 LOS is declared when no marks have been received for one of 15, 31, 63, or 255 consecutive bit periods. J2 LOS is cleared when either 15, 31, 63, or 255 consecutive bit periods have passed without an excessive ...
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Figure 3 Framing Algorithm (CRC_REFR = 0) Reset or Out of Fram e Using this algorithm, the J2-FRMR will on average find frame in 5.07 ms when starting the search in the worst possible position, given a 10 When the ...
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Figure 4 Framing Algorithm (CRC_REFR = 1) Reset or Out of Fram e Using this algorithm, the J2-FRMR will find frame in 10.22 ms, on average when starting the search in the worst possible position, given a 10 algorithm will ...
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J2 extended LOF detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1 ms ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an OOF ...
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The Status register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status register also indicates the abort, flag, and ...
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The PRGD may also be programmed to check for repetitive sequences. When configured to detect a pattern of length N-bits, the PRGD will load N-bits from the detected stream, and determine whether the received pattern repeats itself every N subsequent ...
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The E3-TRAN generates the frame alignment signal and inserts it into the incoming serial stream based on either the G.751 or G.832 formats. All overhead and status bits in each frame format can be individually controlled by register bits or ...
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J2 Transmitter The J2 Transmitter (J2-TRAN) Block integrates circuitry required to insert the overhead bits into an J2 bit stream and produce a B8ZS-encoded signal. The J2-TRAN is directly compatible with the framing format specified in G.704 and NTT ...
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When enabled, the TDPR continuously transmits flags (01111110) until data is ready to be transmitted. Data bytes to be transmitted are written into the TDPR Transmit Data register. The TDPR automatically begins transmission of data once at least one complete ...
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Microprocessor Interface The microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. Normal mode registers are required for normal operation. Test mode registers are used to enhance the testability ...
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Address 035H 135H 235H 036H- 136H- 236H- 037H 137H 237H 038H 138H 238H 039H 139H 239H 03AH 13AH 23AH 03BH 13BH 23BH 03CH 13CH 23CH 03DH 13DH 23DH 03EH 13EH 23EH 03FH 13FH 23FH 040H 140H 240H 041H 141H 241H ...
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Address 05DH 15DH 25DH 05EH- 15EH- 25EH- 05FH 15FH 25FH 090H 180H 290H 091H 181H 291H 092H 182H 292H 093H 183H 293H 094H 184H 294H 095H 195H 295H 096H- 196H- 296H- 097H 197H 297H 098H 198H 298H 099H 199H 299H ...
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Normal Mode Register Descriptions Normal mode registers are used to configure and monitor the operation of the S/UNI-4xD3F. Normal mode registers (as opposed to test mode registers) are selected when A[10] is low. Notes on Normal Mode Register Bits: ...
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Register 000H, 100H, 200H, 300H: S/UNI-4xD3F Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PLOOP The PLOOP bit controls the DS3, ...
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LOOPT The LOOPT bit selects the transmit timing source. When a logic one is written to LOOPT, the transmitter is loop-timed to the receiver. When loop timing is enabled, the receive clock (RCLK) is used as the transmit timing source. ...
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Register 001H, 101H, 201H, 301H: S/UNI-4xD3F Configuration 2 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W RXMFPO The RXMFPO bit controls which ...
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TXMFPI The TXMFPI bit controls which of the inputs TMFPI[4:1] or TFPI[4:1] is valid. If TXMFPI is a logic one, then TMFPI[4:1] will be expected. If TXMFPI is a logic zero, then TFPI[4:1] will be expected. This bit is effective ...
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Register 002H, 102H, 202H, 302H: S/UNI-4xD3F Transmit Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TNEGINV The TNEGINV bit provides polarity ...
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TICLK The TICLK bit selects the transmit clock used to update the TPOS/TDATO and TNEG/TOHM outputs. When a logic zero is written to TICLK, the buffered version of the input transmit clock, TCLK, is used to update TPOS/TDATO and TNEG/TOHM ...
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Register 003H, 103H, 203H, 303H: S/UNI-4xD3F Receive Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W RNEGINV The RNEGINV bit provides polarity ...
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LOFINT[1:0] The LOFINT[1:0] bits determine the integration period used for asserting and de-asserting E3 and DS3 LOF or J2 extended LOF on the FRMLOF register bit of the S/UNI-4xD3FFRMR LOF Status register (x9CH) and on the FRMSTAT[4:1] output pins (if ...
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Register 004H, 104H, 204H, 304H: Data Link and FERF/RAI Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W DLINV The DLINV bit ...
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For G.751 E3 streams, the National Use bit is sourced by the TDPR block if TNETOP and the NATUSE bit (from the E3 TRAN Configuration register x41H) are both logic zero. If either TNETOP or NATUSE is logic one, the ...
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RBLEN The RBLEN-bit enables: the receive RED alarm (persistent OOF) indication to automatically generate a FERF indication in the DS3 transmit stream BIP8 error detection in the E3 G.832 Framer to generate a FEBE indication in the E3 ...
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Register 005H, 105H, 205H, 305H: S/UNI-4xD3F Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R SPLRI/TTBI, RBOCI/PRGDI, FRMRI/LOFI, PMONI, TDPRI, RDLCI ...
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Register 006H: S/UNI-4xD3F Identification, Master Reset, and Global Monitor Update Bit Type Bit 7 R/W Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R This register is used ...
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Register 007H, 107H, 207H, 307H: S/UNI-4xD3F Clock Activity Monitor and Interrupt Identification Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 Bit 0 TICLKA The TICLKA bit ...
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Register 010H, 110H, 210H, 310H: Change of PMON Performance Meters Bit Type Bit 7 Bit 6 Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R FEBECH The FEBECH bit is set ...
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Register 011H, 111H, 211H, 311H: PMON Interrupt Enable/Status Bit Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 R/W Bit 1 R Bit 0 R OVR The OVR bit indicates the overrun status of the PMON ...
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Register 014H, 114H, 214H, 314H: PMON LCV Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 015H, 115H, 215H, ...
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Register 016H, 116H, 216H, 316H: PMON Framing Bit Error Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 017H, ...
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Register 018H, 118H, 218H, 318H: PMON EXZS Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 019H, 119H, 219H, 319H: ...
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Register 01AH, 11AH, 21AH, 31AH: PMON Parity Error Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 01BH, 11BH, ...
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Register 01CH, 11CH, 21CH, 31CH: PMON Path Parity Error Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 01DH, ...
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Register 01EH, 11EH, 21EH, 31EH: PMON FEBE/J2-EXZS Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 01FH, 11FH, 21FH, ...
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Register 030H, 130H, 230H, 330H: DS3 FRMR Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W CBE The CBE bit enables the ...
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M3O8 The M3O8 bit controls the DS3 OOF decision criteria. When a logic one is written to M3O8, DS3 OOF is declared when three of eight framing bits (F-bits) are in error. When a logic zero is written to M3O8, ...
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Register 031H, 131H, 231H, 331H: DS3 FRMR Interrupt Enable (ACE=0) Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LOSE The LOSE bit ...
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REDE The REDE bit enables an interrupt to be generated when a change of state of the DS3 RED indication occurs. The DS3 RED indication is visible in the REDV bit location of the DS3 FRMR Status register. When REDE ...
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Register 031H, 131H, 231H, 331H: DS3 FRMR Additional Configuration Register (ACE=1) Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W DALGO The DALGO bit determines ...
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EXZSO The EXZSO bit enables only summed zero occurrences to be accumulated in the PMON EXZS Count registers. When EXZSO is set to logic one, any excessive zeros occurrences over an 85 bit period increments the PMON EXZS counter by ...
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Table 10 DS3 FRMR AIS Configurations AISPAT AISC Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000314, Issue 5 AISONES AIS Detected X Framed ...
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Register 032H, 132H, 232H, 332H: DS3 FRMR Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R LOSI The LOSI bit is ...
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REDI The REDI bit indicates that a change of state of the DS3 RED indication has occurred. The DS3 RED indication is visible in the REDV bit location of the DS3 FRMR Status register. When the REDI bit is a ...
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Register 033H, 133H, 233H, 333H: DS3 FRMR Status Bit Type Bit 7 R/W Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R LOSV The LOSV bit indicates the ...
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CBITV The CBITV bit indicates the application identification channel (AIC) state. CBITV is set to logic one (indicating the presence of the C-bit parity application) when the AIC bit is set high for 63 consecutive M-frames. CBITV is set to ...
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Register 034H, 134H, 234H, 334H: DS3 TRAN Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 Bit 1 Bit 0 R/W CBIT The CBIT bit enables the DS3 C-bit ...
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CBTRAN The CBTRAN-bit controls the C-bit values during AIS transmission. When CBTRAN is written with a logic zero, the C-bits are overwritten with zeros during AIS transmission as specified in ANSI T1.107. When CBTRAN is written with a logic one, ...
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Register 035H, 135H, 235H, 335H: DS3 TRAN Diagnostic Bit Type Bit 7 R/W Bit 6 R/W Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W DFEBE The DFEBE bit controls the insertion ...
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DLCV The DLCV bit controls the insertion of a single LCV in the DS3 stream. When DLCV is written with a logic one, a LCV is inserted by generating an incorrect polarity of violation in the next B3ZS signature. The ...
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Register 038H, 138H, 238H, 338H: E3 FRMR Framing Options Bit Type Bit 7 Unused Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W REFR A transition from logic zero ...
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UNI The UNI bit selects the mode of the receive data interface. When UNI is logic one, the E3- FRMR expects unipolar data on the RDATI input and accepts LCV indications on the RLCV input. When UNI is logic zero, ...
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Register 039H, 139H, 239H, 339H: E3 FRMR Maintenance Options Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TMARKDET The TMARKDET bit determines the persistency ...
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WORDERR The WORDERR bit selects whether the framing bit error indication pulses accumulated in PMON indicate all bit errors in the framing pattern or only one error for one or more errors in the framing pattern. When WORDERR is logic ...
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Register 03AH, 13AH, 23AH, 33AH: E3 FRMR Framing Interrupt Enable Bit Type Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W OOFE The OOFE bit is an interrupt ...
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Register 03BH, 13BH, 23BH, 33BH: E3 FRMR Framing Interrupt Indication and Status Bit Type Bit 7 Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R OOF The OOF-bit ...
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COFAI The COFAI bit indicates that a change of frame alignment between the previous alignment and the newly found alignment has occurred. When COFAI is logic one, the last high-to-low transition on the OOF signal resulted in the new frame ...
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Register 03CH, 13CH, 23CH, 33CH: E3 FRMR Maintenance Event Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W NATUSEE The NATUSEE ...
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FERFE The FERFE bit is an interrupt enable. When FERFE is logic one, an interrupt is generated on the INTB output when the FERF indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or when the RAI bit ...
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Register 03DH, 13DH, 23DH, 33DH: E3 FRMR Maintenance Event Interrupt Indication Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R NATUSEI The NATUSEI ...
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FERFI The FERFI bit is a transition indication. When FERFI is logic one, a change of state of the FERF indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or when the RAI bit (bit 12 of the ...
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Register 03EH, 13EH, 23EH, 33EH: E3 FRMR Maintenance Event Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R NATUSE The NATUSE bit ...
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AISD The AISD bit reflects the state of the AIS detection circuitry. When AISD is logic one, less than eight zeros (in G.832 mode), or less than 5 zeros (in G.751 mode), were detected during one complete frame period while ...
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Register 040H, 140H, 240H, 340H: E3 TRAN Framing Options Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W FORMAT[1:0] The FORMAT[1:0] bits determine the framing ...
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Register 041H, 141H, 241H, 341H: E3 TRAN Status and Diagnostic Options Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W NATUSE The NATUSE bit ...
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DFERR The DFERR bit selects whether the framing pattern is corrupted for diagnostic purposes. When DFERR is logic one, the framing pattern inserted into the output data stream is inverted. When DFERR is logic zero, the unaltered framing pattern inserted ...
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Register 042H, 142H, 242H, 342H: E3 TRAN BIP-8 Error Mask Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W MBIP[7:0] The MBIP[7:0] bits ...
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Register 043H, 143H, 243H, 343H: E3 TRAN Maintenance and Adaptation Options Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TIMEMK The TIMEMK ...
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FERF/RAI The FERF/RAI bit reflects the value to be inserted in the FERF indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or the value of the RAI bit (bit 11 of the frame in G.751). The FERF/RAI ...
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Register 044H, 144H, 244H, 344H: J2-FRMR Configuration Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W UNI When the UNI bit is set to ...
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SFRME When the Single Framing Bit Error (SFRME) bit is set to logic one, then the J2-FRMR will indicate (to the PMON) a single framing error for every J2 multiframe which contains one or more framing errors. When the SFRME ...
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Register 045H, 145H, 245H, 345H: J2-FRMR Status Bit Type Bit 7 R Bit 6 R Bit 5 Bit 4 R Bit 3 R Bit 2 Bit 1 R Bit 0 R LOS, LOF, RAI, RLOF, PHYAIS, PLDAIS These register bits ...
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Register 046H, 146H, 246H, 346H: J2-FRMR Alarm Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LOSE When LOSE is logic ...
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RLOF_THR The RLOF Threshold bit determines the number of consecutive a-bits that are required for the state of RLOF to change. When RLOF_THR is logic zero, RLOF is asserted when the a-bit has been logic one for three consecutive frames, ...
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Register 047H, 147H, 247H, 347H: J2-FRMR Alarm Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 Bit 1 R Bit 0 R LOSI The LOSI bit is set ...
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PLDAISI The PLDAISI bit is set to logic one if a change in the condition of PLDAIS occurs. PLDAISI is cleared when this register is read. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: ...
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Register 048H, 148H, 248H, 348H: J2-FRMR Error/Xbit Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 Bit 1 R/W Bit 0 R/W CRCEE When CRCEE is logic one, ...
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XBIT_DEB When XBIT_DEB is set to logic zero, the x-bit indications in the J2-FRMR Error/Xbit Interrupt Status register reflect the most recent value of the x-bits. When XBIT_DEB is set to logic one, the x-bit indications change value only when ...
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Register 049H, 149H, 249H, 349H: J2-FRMR Error/Xbit Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R CRCEI The CRCEI bit is ...
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X1, X2, X3 The X1, X2, and X3 bits reflect the most recent (debounced if XBIT_DEB is set to logic one) value of bits 785, 786, and 787 respectively of frame three of each multiframe. These bits are the spare ...
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Register 04CH, 14CH, 24CH, 34CH: J2-TRAN Configuration Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W RLOF The RLOF-bit controls the state of the ...
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Register 04DH, 14DH, 24DH, 34DH: J2-TRAN Diagnostic Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W DFERR The DFERR bit controls the insertion of framing ...
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Register 04EH, 14EH, 24EH, 34EH: J2-TRAN TS97 Signaling Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TS97[1:8] The TS97[1:8] bits control what ...
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Register 04FH, 14FH, 24FH, 34FH: J2-TRAN TS98 Signaling Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TS98[1:8] The TS98[1:8] bits control what ...
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Register 050H, 150H, 250H,350H: RDLC Configuration Bit Type Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W EN The EN-bit controls the overall operation of the RDLC. When ...
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Reserved This register bit should be set to logic zero for proper operation. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000314, Issue 5 S/UNI®-4xD3F Data Sheet Released 130 ...
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Register 051H, 151H, 251H, 351H: RDLC Interrupt Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W INTC[6:0] The INTC[6:0] bits control the ...
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Register 052H, 152H, 252H, 352H: RDLC Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Consecutive reads of the RDLC Status and ...
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PBS[2:0] Data Status 010 The data byte read from the FIFO is the dummy byte that was written into the FIFO when the HDLC abort sequence (01111111) was detected. This indicates that the data link became inactive. 011 Unused. 100 ...
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Register 053H, 153H, 253H, 353H: RDLC Data Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Consecutive reads of the RDLC Status and ...
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Register 054H, 154H, 254H, 354H: RDLC Primary Address Match Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PA[7:0] The first byte received ...
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Register 055H, 155H, 255H, 355H: RDLC Secondary Address Match Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W SA[7:0] The first byte received ...
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Register 058H, 158H, 258H, 358H: TDPR Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Consecutive writes to the TDPR Configuration, TDPR Interrupt ...
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EOM The EOM-bit indicates that the last byte of data written in the Transmit Data register is the end of the present data packet. If the CRC bit is set then the 16-bit FCS word is appended to the last ...
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Register 059H, 159H, 259H, 359H: TDPR Upper Transmit Threshold Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W UTHR[6:0] The UTHR[6:0] bits define the ...
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Register 05AH, 15AH, 25AH, 35AH: TDPR Lower Interrupt Threshold Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LINT[6:0] The LINT[6:0] bits define the ...
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Register 05BH, 15BH, 25BH, 35BH: TDPR Interrupt Enable Bit Type Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LFILLE The LFILLE enables a transition to logic one ...
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Register 05CH, 15CH, 25CH, 35CH: TDPR Interrupt Status/UDR Clear Bit Type Bit 7 Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Consecutive writes to the TDPR Configuration, ...
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BLFILL The BLFILL bit is set to logic one if the current FIFO fill level is below the LINT[7:0] level or is empty. FULL The FULL bit reflects the current condition of the TDPR FIFO. If FULL is a logic ...
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Register 05DH, 15DH, 25DH, 35DH: TDPR Transmit Data Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Consecutive writes to the TDPR Configuration, ...
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Register 090H, 190H, 290H, 390H: TTB Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Reserved The reserved bit should be set ...
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RTIMIE The receive trace identifier mismatch interrupt enable (RTIMIE) controls the activation of the interrupt output when comparison between the accepted trace identifier message and the expected trace identifier message changes state from match to mismatch and vice versa. When ...
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Register 091H, 191H, 291H, 391H: TTB Identifier Status Bit Type Bit 7 R Bit 6 Bit 5 Bit 4 Bit 3 R Bit 2 R Bit 1 R Bit 0 R RTIMV The receive trace identifier mismatch value status bit ...
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Register 092H, 192H, 292H, 392H: TTB Indirect Address Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W A[6:0] The indirect read address bits ...
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Register 093H, 193H, 293H, 393H: TTB Indirect Data Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W D[7:0] The indirect data bits (D[7:0]) ...
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Register 094H, 194H, 294H, 394H: TTB EXPLD Type Label Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W EXPLD[2:0] The EXPLD[2:0] bits contain ...
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Register 095H, 195H, 295H, 395H: TTB Payload Type Label Control/Status Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R RPLDMV The receive payload ...
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RPLDMIE The receive payload type label mismatch interrupt enable bit (RPLDMIE) controls the activation of the interrupt output when the comparison between received and the expected payload type label changes state from match to mismatch and vice versa. When RPLDMIE ...
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Register 098H, 198H, 298H, 398H: RBOC Configuration/Interrupt Enable Bit Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 R/W Bit 1 R/W Bit 0 R/W FEACE The FEACE bit enables the generation of an interrupt when ...
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Register 099H, 199H, 299H, 399H: RBOC Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R FEAC[5:0] The FEAC[5:0] bits contain the ...
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Register 09AH, 19AH, 29AH, 39AH: XBOC Code Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W FEAC[5:0] FEAC[5:0] contain the six bit code that is ...
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Register 09BH, 19BH, 29BH, 39BH: S/UNI-4xD3F Miscellaneous Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LINESYSCLK LINESYSCLK is used to select the ...
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The LOC_RESET bit for quadrant 1 (register 09BH) also resets the chip level Utopia bus. While the LOC_RESET for quadrant 1 is set to logic one, the S/UNI-4xD3F ’s Utopia bus will be held in a reset state, and will ...
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Register 09CH, 19CH, 29CH, 39CH: S/UNI-4xD3F FRMR LOF Status Bit Type Bit 7 R Bit 6 R/W Bit 5 R Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W FRMLOFI The FRMLOFI bit shows ...
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Register 0A0H, 1A0H, 2A0H, 3A0H: PRGD Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PDR[1:0] The PDR[1:0] bits select the content ...
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TINV The TINV bit controls the logical inversion of the generated data stream. When TINV is a logic one, the data is inverted. When TINV is a logic zero, the data is not inverted RINV The RINV bit controls the ...
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Register 0A1H, 1A1H, 2A1H, 3A1H: PRGD Interrupt Enable/Status Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R SYNCE The SYNCE bit enables the ...
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BEI The BEI bit indicates that one or more bit errors have been detected since the last time this register was read. When BEI is set to logic one, at least one bit error has been detected. BEI is set ...
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Register 0A2H, 1A2H, 2A2H, 3A2H: PRGD Length Bit Type Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PL[4:0] PL[4:0] determine the length of the generated pseudo random ...
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Register 0A3H, 1A3H, 2A3H, 3A3H: PRGD Tap Bit Type Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PT[4:0] PT[4:0] determine the feedback tap position of the generated ...
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Register 0A4H, 1A4H, 2A4H, 3A4H: PRGD Error Insertion Bit Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W EVENT A low-to-high transition on the EVENT bit causes a ...
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Register 0A8H, 1A8H, 2A8H, 3A8H: Pattern Insertion #1 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Register 0A9H, 1A9H, 2A9H, 3A9H: Pattern ...
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Register 0AAH, 1AAH, 2AAH, 3AAH: Pattern Insertion #3 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Register 0ABH, 1ABH, 2ABH, 3ABH: Pattern ...
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Register 0ACH, 1ACH, 2ACH, 3ACH: PRGD Pattern Detector #1 Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 0ADH, 1ADH, 2ADH, 3ADH: ...
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Register 0AEH, 1AEH, 2AEH, 3AEH: PRGD Pattern Detector #3 Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 0AFH, 1AFH, 2AFH, 3AFH: ...
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Register 40CH: S/UNI-4xD3F Identification Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R This register provides a device identification to distinguish the S/UNI-4xD3F ...
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Test Features Description The test mode registers, shown in Table 18, are used for production and board testing. During production testing, the test mode registers are used to apply test vectors. In this case, the test mode registers (as ...
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Address 44FH 54FH 64FH 450H 550H 650H 451H 551H 651H 452H 552H 652H 453H 553H 653H 454H 554H 654H 458H 558H 658H 459H 559H 659H 45AH 55AH 65AH 45BH 55BH 65BH 490H 590H 690H 491H 591H 691H 492H 592H 692H ...
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Register 400H: S/UNI-4xD3F Master Test Bit Type Bit 7 Bit 6 W Bit 5 W Bit 4 W Bit 3 W Bit 2 R/W Bit 1 W Bit 0 R/W This register is used to enable S/UNI-4xD3F test features. All ...
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PMCTST The PMCTST bit is used to configure the S/UNI-4xD3F for PMC Sierra's manufacturing tests. When PMCTST is set to logic one, the S/UNI-4xD3F microprocessor port becomes the test access port used to run the PMC manufacturing test vectors. The ...
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Table 21 Boundary Scan Register Note: Length - 198 bits Pin/Enable Register Bit VSS 0 VSS 1 VSS 2 VSS 3 VSS 4 VSS 5 VSS 6 VSS 7 VSS 8 VSS 9 VSS 10 VSS 11 VSS 12 VSS ...
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Pin/Enable Register Bit N/C 36 N/C 37 N/C 38 N/C 39 Reserved 40 N/C 41 VSS 42 VSS 43 VSS 44 VSS 45 VSS 46 VSS 47 VSS 48 N/C 49 N/C 50:65 Notes 1. The DOENB signals will set ...
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Operation 13.1 Software Initialization Sequence Using the following software initialization sequence puts the S/UNI-4xD3F in normal power consumption state. PMC-Sierra™ strongly recommends using this reset sequence to guarantee the device’s long term reliability. Note: After a reset, the S/UNI-4xD3F ...
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° 10000000 to test register 480H ° 10000000 to test register 580H ° 10000000 to test register 680H ° 10000000 to test register 780H ° 10101010 to test register 482H ° 10101010 to test register 582H ° 10101010 to test ...
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Figure 5 DS3 Frame Structure M-subframe X 1 Payload F 1 Payload C 1 Payload Payload F 1 Payload C 1 Payload Payload F 1 Payload C 1 Payload Payload F ...
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Control Bit Transmit Operation F2=0, F3=0, F4=1). M-subframe Alignment Signal Cx: In M23 framer-only mode, passed through transparently. This excludes the C-bit C-Bit Parity ID bit, which toggles every M-frame. Channels M23 Operation C-bit Parity The C-bit Parity ID bit ...
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G.751 E3 Frame Format The S/UNI-4xD3F provides support for the G.751 E3 frame format, shown in Figure 6. Figure 6 G.751 E3 Frame Structure ...
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G.832 E3 Frame Format The S/UNI-4xD3F provides support for the G.832 E3 frame format. The G.832 E3 frame format is shown in Figure 7. Figure 7 G.832 E3 Frame Structure FA1 FA2 The ...
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Control Transmit Operation MA: Inserts the FERF, FEBE, Payload Type bits, Tributary Unit Multiframe Indicator Maintenance bits and the Timing Marker bit as and Adaptation programmed in a register or as indicated Byte by detection of receive OOF or BIP-8 ...
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The J2 transmitter inserts the overhead bits into a J2 bit stream and produces a B8ZS-encoded signal. The J2 transmitter adheres to the framing format specified in G.704 and the NTT Technical Reference for High Speed Digital Leased Circuit Services. ...
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Having identified the quadrant which produced the interrupt, read the S/UNI-4xD3F Interrupt Status register (005H, 105H, 205H, and 305H) to identify which block in the quadrant produced the interrupt. For example, a logic one on the TDPRI register bit ...
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If the block used in interrupt driven mode, then enable interrupts by setting the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register to logic one. 3. Set the TDPR operating parameters in ...
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If more data bytes are to be transmitted in the packet, then go to step b. If all bytes in the packet have been sent, then set the EOM-bit in the TDPR Configuration register to logic one step ...
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If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. When the UDRI bit transitions to logic one, one abort sequence and continuous flags will be transmitted. The TDPR ...
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Upon system power-up, the RDLC should be disabled by setting the EN-bit in the Configuration register to its default of logic zero. The RDLC Interrupt Control register should then be initialized to enable the INT output and to select the ...
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If COLS = 1, then sets the EMPTY FIFO software flag. If PKIN = 1, increments the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software ...
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Figure 9 Typical Data Frame BIT Address (high) CONTRO L Fram e Check Sequence Bit 1 is the first serial bit to be received. When enabled, the primary, ...
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LA is the state of the LINK ACTIVE software flag. At points 1 and 5 the first flag after all-ones or abort is detected. A dummy byte is written in the FIFO, FE goes low, and an interrupt goes ...
Page 193
The pattern generator consists of a 32-bit shift register and a single XOR gate. The XOR gate output is fed into the first stage of the shift register. The XOR gate inputs are determined by values written to the length ...
Page 194
Pattern Type (O.153 (O.152, O.153 (O.151 (O.153 (O.151 QRSS bit= ...
Page 195
The TINV bit and the RINV bit are contained in the PRGD Control register 13.12 JTAG Support The S/UNI-4xD3F supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The TAP consists of the five standard ...
Page 196
The boundary scan architecture consists of: • A TAP controller • An instruction register with instruction decode • A bypass register • A device identification register • A boundary scan register The TAP controller interprets the TMS input and generates ...
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Figure 13 TAP Controller Finite State Machine TRSTB=0 Test-Logic- Reset 1 0 Run-Test- Idle 0 Notes 1. Test-Logic-Reset is the state is used to disable the TAP logic when the device is in normal mode operation. The state is entered ...
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Run-Test-Idle is used to execute tests. 3. Capture-DR is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by ...
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Boundary Scan Cell Description In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending ...
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Figure 16 Bi-directional Cell (IO_CELL) EXTEST OUTPUT from internal logic IDC ODE SHIFT-DR INPUT from pin I.D. code bit CLO CK -DR UPDAT E-DR Scan Chain In Figure 17 Layout of Output Enable and Bi-directional Cells OUTPUT ENABLE from internal ...