HD6417034F20 Renesas Electronics Corporation., HD6417034F20 Datasheet
HD6417034F20
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HD6417034F20 Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SuperH™ RISC Engine SH7032 and SH7034 HD6437034B, ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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The SH7032 and SH7034 are microprocessors that integrate peripheral functions necessary for system configuration with a 32-bit internal architecture SH1-DSP CPU as its core. The SH7032 and SH7034's on-chip peripheral functions include an interrupt controller, timers, serial communication interfaces, a ...
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User's Manuals on the SH7032 and SH7034: Manual Title SH7032 and SH7034 Hardware Manual SH-1, SH-2, SH-DSP Programming Manual Users manuals for development tools: Manual Title C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual Simulator Debugger Users Manual Hitachi Embedded ...
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Organization of This Manual Table 1 describes how this manual is organized. Figure 1 shows the relationships between the sections within this manual. Table 1 Manual Organization Category Section Title Overview 1. Overview CPU 2. CPU Operating 3. Operating Modes ...
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Table 1 Manual Organization (cont) Category Section Title Pins 15. Pin Function Controller 16. Parallel I/O Ports Memory 17. ROM 18. RAM Power-Down 19. Power-Down State State Electrical 20. Electrical Char act Characteristics ...
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CPU 7. Clock pulse generator (CPG) Buses 8. Bus state controller (BSC) 9. Direct memory access controller (DMAC) Memory 17. ROM 18. RAM Pins 15. Pin function controller (PFC) 16. Parallel I/O ports Figure 1 Manual Organization 1. Overview ...
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Addresses of On-Chip Peripheral Module Registers The on-chip peripheral module registers are located in the on-chip peripheral module space (area 5: H'5000000–H'5FFFFFF), but since the actual register space is only 512 bytes, address bits A23–A9 are ignored. 32k shadow areas ...
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... HD6437034AFI20 HD6437034AFI20 HD6437034AVF12 HD6437034AF12 HD6437034AVFI12 HD6437034AFI12 HD6437034AX20 HD6437034ATE20 120-pin plastic TQFP (TFP-120) HD6437034AXI20 HD6437034ATEI20 HD6437 HD6437034ATE12 HD6437034AVXI12 HD6437034ATEI12 HD6417034F20 HD6417034F20 112-pin plastic QFP (FP-112) HD6417034FI20 HD6417034FI20 HD6417034VF12 HD6417034VF12 HD6417034VFI12 HD6417034VFI12 HD6417034X20 HD6417034TE20 120-pin plastic TQFP (TFP-120) HD6417034XI20 HD6417034TEI20 ...
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Section Page Description 2.1.2 Control 18 Description amended Registers Figure 2.2 Control Registers 2.1.4 Initial Values 19 Description amended of Registers Table 2.1 Initial Values of Registers 3.1 Types of 49 Note amended Operating Modes and *2 Only modes 0 ...
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Section Page Description 10.4.6 271 Description amended Complementary 3. Set bits CMD1 and CMD0 in TMDB to select complementary PWM PWM Mode Procedure for Selecting Complementary PWM Mode (Figure 10.33): 10.6.15 ITU 301 Table amended Operating Modes Table 10.18 ITU ...
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Section Page Description 12.2.2 Timer 338 Note added Control/Status Note: * Only 0 can be written, to clear the flag. Register (TCSR) 13.2.6 Serial Control 359 Initial value added Register 13.2.8 Bit Rate 367 Note added Register (BRR) Note: Settings ...
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Section Page Description 19.1.2 Register 460 Note added Table 19.2 Standby Control Register (SBYCR) 20.1.2 DC 467 16.6 MHz deleted Characteristics Table 20.2 DC Characteristics Table 20 Table of 16.6 MHz deleted Characteristics Table 20.3 471 16.6 MHz ...
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Section Page Description 507 16.6 MHz deleted (4) DMAC Timing Table 20.8 DMAC Timing 509 16.6 MHz deleted (5) 16-bit Integrated Timer Pulse Unit Timing Table 20.9 16-bit Integrated Timer Pulse Unit Timing 510 16.6 MHz deleted (6) Programmable Timing ...
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Section Page Description 20.2.1 Absolute 517 Notes amended Maximum Ratings Table 20.15 Absolute Maximum Ratings Table 20.16 DC 518, 12.5 MHz added Characteristics 519 Table 20.17 521 12.5 MHz added Permitted Output Current Values Item Power supply voltage Input voltage ...
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Section Page Description 20.2.3 AC 522 12.5 MHz added and description amended Characteristics 1 Clock Timing Table 20.18 Clock Timing 2 Control Signal 524 12.5 MHz added and description amended Timing Table 20.19 Control Signal Timing 3 Bus Timing 528 ...
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Section Page Description 4 DMAC Timing 546 12.5 MHz added Table 20.21 DMAC Timing 5 16-bit Integrated 547 12.5 MHz added Timer Pulse Unit Timing Table 20.22 16-bit Integrated Timer Pulse Unit Timing 6 Programmable 548 Description amended Timing Pattern ...
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Section Page Description 20.2.4 A/D 554 12.5 MHz added Converter Characteristics Table 20.27 A/D Converter Characteristics A.2.17 Timer Status 581 Bit amended Registers 0–4 (TSR0–TSR4) Table A.18 TSR0– TSR4 Bit Functions A.2.23 Timer Output 587 Table amended Control Register (TOCR) ...
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Section Page Description A.3 Register Status 644 *2 added in Reset and Power- Down States Table A.77 Register Status in Reset and Power-Down States Watchdog timer (WDT) TCNT TCSR RSTCR * 2 Serial communication SMR interface (SCI) BRR SCR TDR ...
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Section 1 Overview ........................................................................................................... 1.1 SuperH Microcomputer Features ...................................................................................... 1.2 Block Diagram................................................................................................................... 1.3 Pin Descriptions................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ 11 1.3.3 Pin Layout by Mode ............................................................................................. 15 Section 2 CPU ..................................................................................................................... 17 2.1 Register Configuration ...................................................................................................... 17 ...
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Exception Handling Types and Priorities............................................................. 51 4.1.2 Exception Handling Operation ............................................................................. 53 4.1.3 Exception Vector Table........................................................................................ 54 4.2 Resets................................................................................................................................. 56 4.2.1 Reset Types .......................................................................................................... 56 4.2.2 Power-On Reset.................................................................................................... 57 4.2.3 Manual Reset........................................................................................................ 57 4.3 Address Errors ................................................................................................................... 58 4.3.1 ...
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Interrupt Control Register (ICR) .......................................................................... 75 5.4 Interrupt Operation ............................................................................................................ 76 5.4.1 Interrupt Sequence................................................................................................ 76 5.4.2 Stack after Interrupt Exception Handling............................................................. 78 5.5 Interrupt Response Time.................................................................................................... 79 5.6 Usage Notes ....................................................................................................................... 80 Section 6 User Break Controller (UBC) 6.1 ...
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Wait State Control Register 1 (WCR1)................................................................ 109 8.2.3 Wait State Control Register 2 (WCR2)................................................................ 111 8.2.4 Wait State Control Register 3 (WCR3)................................................................ 113 8.2.5 DRAM Area Control Register (DCR).................................................................. 114 8.2.6 Refresh Control Register (RCR) .......................................................................... 117 8.2.7 Refresh ...
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Section 9 Direct Memory Access Controller (DMAC) 9.1 Overview............................................................................................................................ 175 9.1.1 Features ................................................................................................................ 175 9.1.2 Block Diagram...................................................................................................... 176 9.1.3 Pin Configuration ................................................................................................. 178 9.1.4 Register Configuration ......................................................................................... 179 9.2 Register Descriptions ........................................................................................................ 180 9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ...
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Timer Control Register (TCR) ............................................................................. 242 10.2.10 Timer I/O Control Register (TIOR) ..................................................................... 244 10.2.11 Timer Status Register (TSR) ................................................................................ 246 10.2.12 Timer Interrupt Enable Register (TIER) .............................................................. 247 10.3 CPU Interface .................................................................................................................... 249 10.3.1 16-Bit Accessible Registers.................................................................................. 249 ...
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Block Diagram...................................................................................................... 310 11.1.3 Input/Output Pins.................................................................................................. 311 11.1.4 Registers ............................................................................................................... 312 11.2 Register Descriptions......................................................................................................... 313 11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2)............................................ 313 11.2.2 Port B Data Register (PBDR)............................................................................... 314 11.2.3 Next Data Register A (NDRA) ...
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Internal Reset With Watchdog Timer .................................................................. 347 Section 13 Serial Communication Interface (SCI) 13.1 Overview............................................................................................................................ 349 13.1.1 Features ................................................................................................................ 349 13.1.2 Block Diagram...................................................................................................... 350 13.1.3 Input/Output Pins.................................................................................................. 351 13.1.4 Register Configuration ......................................................................................... 351 13.2 Register Descriptions......................................................................................................... 352 13.2.1 Receive ...
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A/D Converter Usage Notes.............................................................................................. 423 14.7.1 Setting Analog Input Voltage............................................................................... 423 14.7.2 Handling of Analog Input Pins............................................................................. 423 14.7.3 Switchover between Analog Input and General Port Functions .......................... 424 Section 15 Pin Function Controller (PFC) 15.1 Overview............................................................................................................................ 425 15.2 ...
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Section 19 Power-Down State 19.1 Overview............................................................................................................................ 459 19.1.1 Power-Down Modes............................................................................................. 459 19.1.2 Register................................................................................................................. 460 19.2 Standby Control Register (SBYCR).................................................................................. 460 19.3 Sleep Mode........................................................................................................................ 461 19.3.1 Transition to Sleep Mode ..................................................................................... 461 19.3.2 Exiting Sleep Mode .............................................................................................. 461 19.4 Standby Mode.................................................................................................................... ...
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AC Characteristics Test Conditions............................................................. 553 20.2.4 A/D Converter Characteristics.............................................................................. 554 Appendix A On-Chip Supporting Module Registers A.1 List of Registers................................................................................................................. 555 A.2 Register Tables .................................................................................................................. 565 A.2.1 Serial Mode Register (SMR) SCI......................................................................... 565 A.2.2 Bit Rate Register (BRR) SCI................................................................................ ...
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A.2.38 Break Address Mask Register L (BAMRL) UBC................................................ 604 A.2.39 Break Bus Cycle Register (BBR) UBC................................................................ 605 A.2.40 Bus Control Register (BCR) BSC........................................................................ 606 A.2.41 Wait State Control Register 1 (WCR1) BSC ....................................................... 607 A.2.42 Wait State Control Register 2 ...
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A.2.74 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different) ......... 642 A.2.75 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 ...
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SuperH Microcomputer Features SuperH microcomputers (SH7000 series) comprise a new generation of reduced instruction set computers (RISC) in which a Hitachi-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The CPU has ...
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Table 1.1 Features of the SH7032 and SH7034 Microcomputers Feature Description CPU Original Hitachi architecture 32-bit internal data paths General-register machine: Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers RISC-type instruction set: Instruction length: 16-bit fixed ...
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Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description Nine external interrupt pins (NMI, IRQ0–IRQ7) Interrupt controller (INTC) Thirty-one internal interrupt sources Sixteen programmable priority levels User break controller Generates an interrupt when the CPU or DMAC ...
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Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description Direct memory Permits DMA transfer between the following modules: access External memory controller (DMAC) External I/O (4 channels) On-chip memory Peripheral on-chip modules (except DMAC) DMA transfer can ...
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Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description I/O ports Total of 40 I/O lines (32 input/output lines, 8 input-only lines): Port A: 16 input/output lines (input or output can be selected for each bit) Port ...
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... HD6 HD6 HD6437034AF20 112-pin plastic QFP (FP-112) HD6437034AFI20 HD6437034AF12 HD6437034ATE20 120-pin plastic TQFP (TFP-120) HD6437034ATEI20 HD6437034ATE12 HD6417034F20 112-pin plastic QFP (FP-112) HD6417034FI20 HD6417034VF12 HD6417034VFI12 HD6417034TE20 120-pin plastic TQFP (TFP-120) HD6417034TEI20 HD6417034VTE12 HD6417034VTEI12 ...
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Table 1.2 Product Lineup (cont) Product On-Chip Operating Operating Number ROM Voltage Frequency SH7034B * 1 Mask 3 12.5 MHz -20 to +75 C ROM ROMless 3 MHz Notes: *1 The electrical characteristics ...
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Block Diagram RES WDTOVF MD2 MD1 MD0 NMI CK EXTAL XTAL * ...
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Pin Descriptions 1.3.1 Pin Arrangement ref PC0/AN0 87 PC1/AN1 88 PC2/AN2 89 PC3/AN3 PC4/AN4 92 PC5/AN5 93 PC6/AN6 94 PC7/AN7 PB0/TP0/TIOCA2 97 PB1/TP1/TIOCB2 ...
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ref 93 PC0/AN0 94 PC1/AN1 PC2/AN2 95 96 PC3/AN3 PC4/AN4 98 PC5/AN5 99 100 PC6/AN6 101 PC7/AN7 V 102 SS PB0/TP0/TIOCA2 103 *3 104 NC 105 PB1/TP1/TIOCB2 V 106 CC 107 PB2/TP2/TIOCA3 ...
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Pin Functions Table 1.3 describes the pin functions. Table 1.3 Pin Functions Pin No. Type Symbol (FP-112) Power V 15, 43, 70 83, 84 12, 22, SS 31, 40, 52, 61, ...
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Table 1.3 Pin Functions (cont) Pin No. Type Symbol (FP-112) Operating MD2, 82, 81, 80 mode MD1, control MD0 Interrupts NMI 76 IRQ0– 66–69, 111, 112 IRQ7 IRQOUT 63 Address A21–A0 47–44, 42, bus 41, 39–32, 30–23 Data ...
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Table 1.3 Pin Functions (cont) Pin No. Type Symbol (FP-112) WAIT Bus control 56 (cont) RAS 54 CASH 49 CASL WRH 58 WRL 57 CS0– 48–51, CS7 53– HBS, 23, 58 LBS WR 57 DREQ0, ...
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Table 1.3 Pin Functions (cont) Pin No. Type Symbol (FP-112) TIOCA4, 102, 103 16-bit TIOCB4 integrated timer pulse TOCXA4, 104, 105 unit (ITU) TOCXB4 TCLKA– 66, 67, 104, TCLKD 105 TP15– Timing TP0 112–107, pattern 105–100, controller 98, ...
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Pin Layout by Mode Table 1.4 Pin Layout by Mode Pin No. Pin No. (FP-112) (TFP-120) MCU Mode — PB14/TP14/IRQ6 2 3 PB15/TP15/IRQ7 AD0 5 6 AD1 6 7 ...
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Table 1.4 Pin Layout by Mode (cont) Pin No. Pin No. (FP-112) (TFP-120) MCU Mode — PA4/WRL (WR PA5/WRH (LBS PA6/ PA7/BACK PA8/BREQ 63 ...
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Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers (Rn) General registers Rn consist of sixteen 32-bit registers (R0–R15). General registers are used for data ...
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Control Registers Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR ...
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System Registers System registers consist of four 32-bit registers: multiply and accumulate registers high and low (MACH and MACL), procedure register (PR), and program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. ...
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Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when stored into a ...
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Immediate Data Format Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword data. Immediate data accessed by the TST, ...
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Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory, data is loaded into to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: ...
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Table 2.5 Immediate Data Accessing Classification SH7000 Series CPU 8-bit immediate MOV 16-bit immediate MOV.W ......... .DATA.W H'1234 32-bit immediate MOV.L ......... .DATA.L H'12345678 Note: The address of the immediate data is accessed by @(disp, PC). Absolute Address: When data ...
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Addressing Modes Addressing modes and effective address calculation are described in table 2.8. Table 2.8 Addressing Modes and Effective Addresses Addressing Mnemonic Mode Expression Direct Rn register addressing Indirect @Rn register addressing Post-incre- @Rn + ment indirect register addressing ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression Indirect @(disp:4, Rn) register addressing with displace- ment Indirect @(R0, Rn) indexed register addressing Indirect @(disp:8, GBR GBR) addressing with displace- ment Indirect @(R0, GBR) indexed GBR addressing ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression PC relative @(disp:8, PC) addressing with dis- placement PC relative disp:8 addressing disp:12 26 Effective Addresses Calculation The effective address is the PC value plus an 8-bit displacement ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression Immediate #imm:8 addressing #imm:8 #imm:8 2.3.3 Instruction Formats The instruction format refers to the source operand and the destination operand. The meaning of the operand depends on the ...
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Table 2.9 Instruction Formats Instruction Format 0 format 15 xxxx xxxx xxxx xxxx n format 15 xxxx nnnn xxxx xxxx m format 15 xxxx mmmm xxxx xxxx 28 Destination Source Operand Operand — — 0 — nnnn: Register direct 0 ...
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Table 2.9 Instruction Formats (cont) Instruction Format nm format 15 xxxx nnnn xxxx mmmm md format 15 xxxx xxxx mmmm dddd nd4 format 15 xxxx xxxx nnnn dddd nmd format 15 xxxx dddd nnnn mmmm Destination Source Operand Operand mmmm: ...
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Table 2.9 Instruction Formats (cont) Instruction Format d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd i format 15 xxxx xxxx ...
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Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists instructions by classification. Table 2.10 Classification of Instructions Classifi- Operation cation Types Code Data 5 MOV transfer MOVA MOVT SWAP XTRCT Arithmetic 17 ADD operations ADDC ADDV CMP/cond DIV1 ...
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Table 2.10 Classification of Instructions (cont) Classifi- Operation cation Types Code Logic oper- 6 TST ations XOR (cont) Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BSR JMP JSR RTS System ...
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The following tables (arranged by instruction classification) show instruction codes, operations, and execution states, using the format shown below. Table 2.11 Instruction Code Format Item Format Instruction SRC,DEST OP: Operation code OP.Sz mnemonic Instruction MSB LSB code Operation , summary ...
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Table 2.12 Data Transfer Instructions Instruction Instruction Code 1110nnnniiiiiiii #imm MOV #imm,Rn 1001nnnndddddddd (disp MOV.W @(disp,PC),Rn 1101nnnndddddddd (disp MOV.L @(disp,PC),Rn 0110nnnnmmmm0011 Rm MOV Rm,Rn 0010nnnnmmmm0000 Rm MOV.B Rm,@Rn 0010nnnnmmmm0001 Rm MOV.W Rm,@Rn 0010nnnnmmmm0010 Rm MOV.L Rm,@Rn 0110nnnnmmmm0000 (Rm) MOV.B @Rm,Rn ...
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Table 2.12 Data Transfer Instructions (cont) Instruction MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 MOVT Rn SWAP.B Rm,Rn SWAP.W ...
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Table 2.13 Arithmetic Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PZ Rn 0100nnnn00010001 ...
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Table 2.13 Arithmetic Instructions (cont) Instruction Instruction Code EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MULS Rm,Rn 0010nnnnmmmm1111 MULU Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn ...
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Table 2.14 Logic Operation Instructions Instruction AND Rm,Rn AND #imm,R0 AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm NOT Rm,Rn OR Rm,Rn OR #imm,R0 #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm OR.B TAS.B @Rn TST Rm,Rn TST #imm,R0 TST.B #imm,@(R0,GBR) ...
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Table 2.15 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 ...
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Table 2.17 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L ...
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Table 2.17 System Control Instructions (cont) Instruction Instruction Code STS MACL,Rn 0000nnnn00011010 STS PR,Rn 0000nnnn00101010 STS.L MACH,@– 0100nnnn00000010 Rn STS.L MACL,@– 0100nnnn00010010 Rn STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Note: The execution cycles shown in the table are minimums. The ...
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Operation Code Map Table 2.18 shows an operation code map. Table 2.18 Operation Code Map Instruction Code Fx: 0000 MSB MD: 00 LSB 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn Fx 0010 STC 0000 Rn Fx ...
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Table 2.18 Operation Code Map (cont) Instruction Code Fx: 0000 MSB LSB MD: 00 0100 Rn Fx 0011 STC.L SR,@–Rn 0100 Rn Fx 0100 ROTL 0100 Rn Fx 0101 ROTR 0100 Rm Fx 0110 LDS.L @Rm+,MACH 0100 Rm Fx 0111 ...
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Table 2.18 Operation Code Map (cont) Instruction Code Fx: 0000 MSB MD: 00 LSB 1100 00MD imm/disp MOV.B R0,@ (disp:8,GBR) 1100 01MD disp MOV.B @(disp:8, GBR),R0 1100 10MD imm TST #imm:8,R0 1100 11MD imm TST.B #imm:8, @(R0,GBR) 1101 Rn disp ...
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CPU State 2.5.1 State Transitions The CPU has five processing states: reset, exception handling, bus-released, program execution and power-down. The transitions between the states are shown in figure 2.6. For more information on the reset and exception handling states, ...
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From any state when RES = 0 and NMI = 1 Power-on reset state When an interrupt source or DMA address error occurs Bus request Bus-release-state Bus request generated Bus request generated Bus request cleared Sleep mode Figure 2.6 Transitions ...
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Reset State: In the reset state the CPU is reset. This occurs when the RES pin level goes low. When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur. ...
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Power-Down State In addition to the ordinary program execution states, the CPU also has a power-down state in which CPU operation halts and power consumption is reduced There are two power-down state modes: sleep mode and standby mode. Sleep ...
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Section 3 Operating Modes 3.1 Types of Operating Modes and Their Selection The SH7032 microcomputer operates in one of two operating modes (modes 0 and 1) and the SH7034 operates in one of four operating modes (modes ...
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50 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priorities As figure 4.1 indicates, exception handling may be caused by a reset, address error, interrupt, or instruction. Exception sources are prioritized as indicated in figure 4.1. If two ...
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Reset Address error Interrupt Exception source Instruction Notes: *1 The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and TRAPA. *2 The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE. Figure ...
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Exception Handling Operation Exception sources are detected at the times indicated in table 4.1, whereupon handling starts. Table 4.1 Exception Source Detection and Start of Handling Exception Type Reset Power-on Manual Address error Interrupt Instruction Trap instruction Starts when ...
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Exception Vector Table Before exception handling can execute, the exception vector table must be set in memory. The exception vector table holds the start addresses of exception handling routines (the table for reset exception handling stores initial PC and ...
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Table 4.2 Exception Vector Table Exception Source Power-on reset Manual reset General illegal instruction (Reserved for system use) Illegal slot instruction (Reserved for system use) CPU address error DMA address error Interrupts (Reserved for system use) Trap instruction (user vectors) ...
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Table 4.3 Calculation of Exception Vector Table Addresses Exception Source Reset Address error, interrupt, instructions Note: VBR: Vector base register. For vector table address offsets and vector numbers, see table 4.2. 4.2 Resets 4.2.1 Reset Types A reset is the ...
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Power-On Reset When the NMI pin is high, a low input at the RES pin drives the chip into the power-on reset state. The RES pin should be driven low while the clock pulse generator (CPG) is stopped (or ...
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Address Errors 4.3.1 Address Error Sources Address errors occur during instruction fetches and data reading/writing as shown in table 4.5. Table 4.5 Address Error Sources Bus Cycle Type Bus Master Instruction fetch CPU Data read/write CPU or DMAC Note: ...
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Interrupts 4.4.1 Interrupt Sources Table 4.6 lists the types of interrupt exception handling sources (NMI, user break, IRQ, on-chip supporting module). Table 4.6 Interrupt Sources Interrupt Requesting Pin or Module NMI NMI pin (external input) User break User break ...
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Table 4.7 Interrupt Priority Rankings Type NMI User break IRQ and on-chip supporting modules 4.4.3 Interrupt Exception Handling When an interrupt is generated, the INTC ascertains the interrupt ranking. NMI is always accepted, but other interrupts are only accepted if ...
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Instruction Exceptions 4.5.1 Types of Instruction Exceptions Table 4.8 shows the three types of instruction that start exception handling (trap instructions, illegal slot instructions, and general illegal instructions). Table 4.8 Types of Instruction Exceptions Type Source Instruction Trap instruction ...
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Illegal Slot Instruction An instruction located immediately after a delayed branch instruction is called an “instruction placed in a delay slot.” undefined instruction is located in a delay slot, illegal slot instruction exception handling begins executing when ...
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Cases in which Exceptions are Not Accepted In some cases, address errors and interrupts that directly follow a delayed branch instruction or interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this occurs, the exception is ...
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Stack Status after Exception Handling Table 4.10 shows the stack after exception handling. Table 4.10 Stack after Exception Handling Type Stack Status Address Address of error instruction SP after instruc- tion that has finished executing SR Trap Address of ...
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Notes 4.8.1 Value of the Stack Pointer (SP) An address error occurs if the stack is accessed for exception handling when the value of the stack pointer (SP) is not a multiple of four. Therefore, a multiple of four ...
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66 ...
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Section 5 Interrupt Controller (INTC) 5.1 Overview The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These registers handle interrupt requests according ...
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IRQOUT NMI IRQ0 IRQ1 Input IRQ2 control IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 (Interrupt request) UBC (Interrupt request) DMAC (Interrupt request) ITU (Interrupt request) SCI (Interrupt request) PRT (Interrupt request) A/D (Interrupt request) WDT (Interrupt request) REF ICR UBC: User break ...
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Pin Configuration INTC pins are summarized in table 5.1. Table 5.1 INTC Pin Configuration Name Nonmaskable interrupt input pin NMI Interrupt request input pins Interrupt request output pin 5.1.4 Registers The interrupt controller has six registers as listed in ...
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Interrupt Sources There are four types of interrupt sources: NMI, user break, IRQ, and on-chip supporting module interrupts. Interrupt rankings are expressed as priority levels (0–16), with 0 the lowest and 16 the highest. An interrupt set to level ...
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On-Chip Interrupts On-chip interrupts are interrupts generated by the following 6 on-chip supporting modules: Direct memory access controller (DMAC) 16-bit integrated timer pulse unit (ITU) Serial communication interface (SCI) Bus state controller (BSC) A/D converter (A/D) Watchdog timer (WDT) ...
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Table 5.3 Interrupt Exception Vectors and Rankings Interrupt Pri- ority Order Interrupt Source (Initial Value) NMI 16 User break 15 IRQ0 0–15 (0) IRQ1 0–15 (0) IRQ2 0–15 (0) IRQ3 0–15 (0) IRQ4 0–15 (0) IRQ5 0–15 (0) IRQ6 0–15 ...
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Table 5.3 Interrupt Exception Vectors and Rankings (cont) Interrupt Pri- ority Order Interrupt Source (Initial Value) ITU3 IMIA3 0–15 (0) IMIB3 OVI3 Reserved ITU4 IMIA4 0–15 (0) IMIB4 OVI4 Reserved SCI0 ERI0 0–15 (0) RxI0 TxI0 TEI0 SCI1 ERI1 0–15 ...
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Register Descriptions 5.3.1 Interrupt Priority Registers A–E (IPRA–IPRE) The five registers IPRA–IPRE are 16-bit read/write registers that assign priority levels from 0–15 to the IRQ and on-chip supporting module interrupt sources. Interrupt request sources are mapped onto IPRA–IPRE as ...
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Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input detection mode of external interrupt input pins NMI and IRQ0–IRQ7, and indicates the input signal level at the NMI pin. A reset initializes ICR but standby ...
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Interrupt Operation 5.4.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 5.2 shows a flowchart of the operations up to acceptance of the interrupt. 1. The interrupt request sources send interrupt request signals to the interrupt ...
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Program execution state No Interrupt? Yes No NMI? Yes User break? IRQOUT low *1 Push SR onto stack Push PC onto stack Copy level of accep- tance from IRQOUT high *2 Read exception vector table Branch to ...
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Stack after Interrupt Exception Handling Figure 5.3 shows the stack after interrupt exception handling. Address 4n–8 4n–6 4n–4 4n–2 4n Notes: Bus width is 16 bits stores the start address of the next instruction (return instruction) after ...
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Interrupt Response Time Table 5.5 shows the interrupt response time, which is the time from the occurrence of an interrupt request until interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins. Figure ...
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IRQ Instruction (instruction replaced by interrupt exception handling) Overrun fetch Interrupt service routine— first instruction When m3, the interrupt response time is 11 cycles. F (Instruction fetch) D (Instruction decoding) E (Instruction execution) M (Memory access) ...
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Section 6 User Break Controller (UBC) 6.1 Overview The user break controller (UBC) simplifies the debugging of user programs. Break conditions are set in the UBC and a user break interrupt request is sent to the CPU in response to ...
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Block Diagram Figure 6.1 shows a block diagram of the user break controller. Module bus BBR BAMRH BAMRL Break condition comparator User break interrupt generating circuit UBC BARH, BARL: Break address registers H and L BAMRH, BAMRL: Break address ...
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Register Configuration The user break controller has five registers as listed in table 6.1. These registers are used for setting break conditions. Table 6.1 User Break Controller Registers Name Break address register high Break address register low Break address ...
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Register Descriptions 6.2.1 Break Address Registers (BAR) There are two break address registers—break address register H (BARH) and break address register L (BARL)—that together form a single group. Both are 16-bit read/write registers. BARH stores the upper bits (bits ...
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Break Address Mask Register (BAMR) The two break address mask registers—break address mask register H (BAMRH) and break address mask register L (BARML)—together form a single group. Both are 16-bit read/write registers. BAMRH determines which of the bits in ...
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Break Bus Cycle Register (BBR) The break bus cycle register (BBR 16-bit read/write register that selects the following four break conditions: CPU cycle or DMA cycle Instruction fetch or data access Read or write Operand size (byte, ...
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Bits 5 and 4 (Instruction Fetch/Data Access Select (ID1, ID0)): ID1 and ID0 select whether to break on instruction fetch and/or data access bus cycles. Bit 5: ID1 Bit 4: ID0 Bits 3 and ...
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Operation 6.3.1 Flow of User Break Operation The flow from setting of break conditions to user break interrupt exception handling is described below. 1. Break conditions are set in the break address register (BAR), break address mask register (BAMR), ...
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BARH/BARL Internal address bits 31–0 CD1 CD0 CPU cycle DMA cycle ID1 ID0 Instruction fetch Data access RW1 RW0 Read cycle Write cycle SZ1 SZ0 Byte size Word size Longword size Figure 6.2 Break Condition Logic BAMRH/BAMRL ...
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Break on Instruction Fetch Cycles to On-Chip Memory On-chip memory (on-chip ROM (SH7034 only) and RAM) is always accessed 32 bits each bus cycle. Two instructions are therefore fetched in a bus cycle from on-chip memory . Although only ...
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Setting User Break Conditions CPU Instruction Fetch Bus Cycle: Register settings: BARH = H'0000, BARL = H'0404, BBR = H'0054 Conditions set: Address = H'00000404, bus cycle = CPU, instruction fetch, read (operand size not included in conditions) A ...
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Notes 6.5.1 On-Chip Memory Instruction Fetch Two instructions are simultaneously fetched from on-chip memory break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so ...
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Instruction Fetch Break If a break is attempted at the task A return destination instruction fetch, task B is activated before the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is handled after ...
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94 ...
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Section 7 Clock Pulse Generator (CPG) 7.1 Overview The SuperH microcomputer has a built-in clock pulse generator (CPG) that supplies the chip and external devices with a clock pulse. The CPG makes the chip run at the oscillation frequency of ...
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=10– Figure 7.2 Connection of Crystal Resonator (Example) Table 7.1 Damping Resistance Frequency [MHz Crystal Resonator: Figure 7.3 shows an equivalent circuit of the crystal resonator. Use a crystal ...
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External Clock Input An external clock signal can be input at the EXTAL pin as shown in figure 7.4. The XTAL pin should be left open. The frequency must be equal to the system clock (CK) frequency. The specifications ...
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Usage Notes Board Design: When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Route no other signal lines near the XTAL and EXTAL pin signal lines ...
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Input duty * Note: * With the SH7034B, compensation is performed in the input duty range of 60% to 40%. Figure 7.7 Duty Cycle Correction Circuit Standard Characteristics 2 ...
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100 ...
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Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides address space and outputs control signals for all kinds of memory and peripheral chips. BSC functions enable the chip to be connected directly to DRAM, SRAM, ...
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Block Diagram Figure 8.1 shows a block diagram of the bus state controller. WAIT RD WRH, WRL HBS, LBS AH CS7 to CS0 CASH, CASL RAS CMI interrupt request DPH, DPL PEI interrupt request Interrupt controller WCR: Wait state ...
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Pin Configuration Table 8.1 shows the BSC pin configuration. Table 8.1 Pin Configuration Name Abbreviation CS7–CS0 Chip select 7–0 RD Read WRH High write WRL Low write Write HBS * 2 High byte strobe LBS * ...
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Register Configuration The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM interface, and parity check. Table 8.2 Register Configuration Name Bus control register Wait state control register 1 Wait state control register ...
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Overview of Areas The SH microprocessors have a 32-bit address space in the architecture, but the upper 4 bits are ignored. Table 8.3 outlines the space divisions. As shown, the space is divided into areas 0–7 according to the ...
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Table 8.3 Overview of Space Divisions Area Address 0 H'0000000–H'0FFFFFF 1 H'1000000–H'1FFFFFF 2 H'2000000–H'2FFFFFF 3 H'3000000–H'3FFFFFF 4 H'4000000–H'4FFFFFF 5 H'5000000–H'5FFFFFF 6 H'6000000–H'6FFFFFF 7 H'7000000–H'7FFFFFF 0 H'8000000–H'8FFFFFF 1 H'9000000–H'9FFFFFF 2 H'A000000–H'AFFFFFF 3 H'B000000–H'BFFFFFF 4 H'C000000–H'CFFFFFF 5 H'D000000–H'DFFFFFF 6 H'E000000–H'EFFFFFF 7 H'F000000–H'FFFFFFF ...
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Register Descriptions 8.2.1 Bus Control Register (BCR) The bus control register (BCR 16-bit read/write register that selects the functions of areas and status of bus cycles initialized to H'0000 by a power-on reset, but is ...
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Bit 13 (Warp Mode Bit (WARP)): WARP selects warp or normal mode. 0 sets normal mode and 1 sets warp mode. In warp mode, some external accesses are carried out in parallel with internal access. Bit 13: WARP Description 0 ...
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Wait State Control Register 1 (WCR1) Wait state control register 16-bit read/write register that controls the number of states for accessing each area and whether wait states are used. WCR1 is initialized to H'FFFF by a ...
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Table 8.4 summarizes read cycle state information. Table 8.4 Read Cycle States WAIT Pin Bits 15–8: Input External Memory RW7–RW0 Signal Space 0 Not Areas 1, 3–5,7: 1 sampled state, fixed during Areas state read + ...
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Wait State Control Register 2 (WCR2) Wait state control register 16-bit read/write register that controls the number of states for accessing each area with a DMA single address mode transfer and whether wait states are used. ...
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Table 8.5 Single-Mode DMA Memory Read Cycle States (External Memory Space) WAIT Pin Input Bits 15–8: DRW7–DRW0 Signal 0 Not sampled during single-mode DMA memory read cycle * 1 Sampled during single-mode DMA memory read cycle (Initial value) Note: * ...
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Table 8.6 Single-Mode DMA Memory Write Cycle States (External Memory Space) WAIT Pin Input Bits 15–8: DWW7–DWW0 Signal 0 Not sampled during single-mode DMA memory write cycle * 1 Sampled during single-mode DMA memory write cycle (Initial value) Note: * ...
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Bits 14 and 13 (Long Wait Insertion in Areas 0 and 2, Bits 1, 0 (A02LW1 and A02LW0)): A02LW1 and A02LW0 select the long wait states to be inserted (1–4 states) when accessing external memory space of areas 0 and ...
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Bit: 7 Bit name: — Initial value: 0 R/W: — Bit 15 (Dual-CAS or Dual-WE Select Bit (CW2)): When accessing a 16-bit bus width space, CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the CASH, CASL, ...
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Bit 12: BE Description 0 Normal mode: full access 1 Burst operation: high-speed page mode Bit 11 (CAS Duty (CDTY)): CDTY selects 35% or 50% of the TC state as the high-level duty ratio of the signal CAS in short-pitch ...
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Refresh Control Register (RCR) The refresh control register (RCR 16-bit read/write register that controls the start of refresh- ing and selects the refresh mode and the number of wait states during refreshing initialized to H'0000 ...
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Bit 6: RMODE Description 0 CAS-before-RAS refresh 1 Self-refresh Bits 5 and 4—CBR Refresh Wait State Insertion Bits 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted (1–4) during CAS-before-RAS refreshing. When CBR ...
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Bits 15–8 (Reserved): These bits are always read as 0. Bit 7 (Compare Match Flag (CMF)): Indicates whether the values of RTCNT and the refresh time constant register (RTCOR) match. When 0, the value of RTCNT and RTCOR do not ...
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Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT 16-bit read/write register that is used as an 8-bit upcounter that generates refresh or interrupt requests. When the input clock is selected by clock select bits 2– 0 ...
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RTCOR is initialized to H'00FF by a power-on reset, but is not initialized by a manual reset or in standby mode. To prevent RTCOR from being written incorrectly, it must be written by a different method from most other registers. ...
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Bit 15 (Parity Error Flag (PEF)): When a parity check is carried out, PEF indicates whether a parity error has occurred. 0 indicates that no parity error has occurred; 1 indicates that a parity error has occurred. Bit 15: PEF ...
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Notes on Register Access RCR, RTCSR, RTCNT, and RTCOR differ from other registers in being more difficult to write. Data requires a password when it is written. This prevents data from being mistakenly overwritten by program overruns and so ...
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Address Space Subdivision 8.3.1 Address Spaces and Areas Figure 8.3 shows the address format used in this chip. A31–A28 A27 A26–A24 Basic bus width selection: Not output externally, but used for basic bus width selection When 0, (H'0000000–H'7FFFFFF), the ...
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Table 8.7 How Space is Divided Area Address 0 H'0000000–H'0FFFFFF 1 H'1000000–H'1FFFFFF 2 H'2000000–H'2FFFFFF 3 H'3000000–H'3FFFFFF 4 H'4000000–H'4FFFFFF 5 H'5000000–H'5FFFFFF 6 H'6000000–H'6FFFFFF 7 H'7000000–H'7FFFFFF 0 H'8000000–H'8FFFFFF 1 H'9000000–H'9FFFFFF 2 H'A000000–H'AFFFFFF 3 H'B000000–H'BFFFFFF 4 H'C000000–H'CFFFFFF 5 H'D000000–H'DFFFFFF 6 H'E000000–H'EFFFFFF 7 H'F000000–H'FFFFFFF ...
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As figure 8.4 shows, specific spaces such as DRAM space and address/data multiplexed I/O space are allocated to the 8 areas. Each of the spaces is equipped with the necessary interfaces. The control signals needed by DRAM and peripheral chips ...
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Table 8.8 A26–A24 Bits and Chip Select Signals Address A26 A25 A24 The chip select signal is output only for external accesses. When accessing the on-chip ...
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Logical address space H'B000000 H'3000000 H'B3FFFFF H'B400000 H'33FFFFF H'3400000 H'B7FFFFF H'B800000 H'37FFFFF H'3800000 H'BBFFFFF H'BC00000 H'3BFFFFF H'3C00000 H'BFFFFFF H'3FFFFFF 16-bit space Logical address space H'3000000 H'3200000 H'33FFFFF H'3400000 H'3600000 H'37FFFFF H'3800000 H'3A00000 H'3BFFFFF H'3C00000 H'3E00000 H'3FFFFFF b. Actual space accessed ...
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Area Descriptions Area 0: Area area with address bits A26–A24 set to 000 and an address range of H'0000000–H'0FFFFFF and H'8000000–H'8FFFFFF. Figure 8.5 shows a memory map of area 0. Area 0 can be set for ...
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Logical address space H'8000000 H'800FFFF H'0000000 H'8010000 Shadow H'000FFFF Shadow H'0010000 Shadow H'8FF0000 Shadow H'8FFFFFF Shadow H'0FF0000 Shadow H'0FFFFFF 32-bit space 32-bit space MD2–MD0 = 010 Note: The bus width of area 0 is determined by the MD2–MD0 pins regardless ...
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DRAM control register (DCR) is set use the address multiplex function, bits A23–A0 are multiplexed and output from pins A15–A0 maximum 16-Mbyte space can be used. When DRAM space is accessed, the CS1 signal is ...
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Areas 2–4 are always used as external memory space. The bus width is 8 bits when the A27 bit is 0 and 16 bits when A23 and A22 bits are not output and the shadow is in ...
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Area 5: Area area with address bits A26–A24 set to 101 and an address range of H'5000000–H'5FFFFFF and H'D000000–H'DFFFFFF. Figure 8.8 shows a memory map of area 5. Area 5 is allocated to on-chip supporting module space ...
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Area 6: Area area with address bits A26–A24 set to 110 and an address range of H'6000000–H'6FFFFFF and H'E000000–H'EFFFFFF. Figure 8.9 shows a memory map of area 6. In area 6, a space for which address bit ...
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Area 7: Area area with address bits A26–A24 set to 111 and an address range of H'7000000–H'7FFFFFF and H'F000000–H'FFFFFFF. Figure 8.10 shows a memory map of area 7. Area 7 is allocated to external memory space when ...
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Accessing External Memory Space In external memory space, a strobe signal is output based on the assumption of a directly connected SRAM. The external memory space is allocated to the following areas: Area 0 (when MD2–MD0 are 000 or ...
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CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.12 Basic Timing of External Memory Space Access (2-State Read Timing) High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit ...
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Wait State Control The number of external memory space access states and the insertion of wait states can be controlled using the WCR1–WCR3 bits. The bus cycles that can be controlled are the CPU read cycle and the DMAC ...
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CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 WAIT Figure 8.13 Wait State Timing for External Memory Space Access (2 States Plus Wait Areas 0, 2, and 6 have long wait functions. When the corresponding bits in WCR1 ...
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CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 WAIT Figure 8.14 Wait State Timing for External Memory Space Access (1 State Plus Long Wait State (When Set to Insert 3 States) Plus Wait States from WAIT Signal) For ...
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Byte Access Control The upper byte and lower byte control signals when 16-bit bus width space is being accessed can be selected from (WRH, WRL, A0) or (WR, HBS, LBS). When the byte access select bit (BAS) in BCR ...
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DRAM Interface Operation When the DRAM enable bit (DRAME) in BCR is set to 1, area 1 becomes DRAM space and the DRAM interface function is available, which permits direct connection of this chip to DRAMs. 8.5.1 DRAM Address ...
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Table 8.10 Relationship between Multiplex Shift Count Bits (MXC1, MXC0) and Address Multiplexing 8-Bit Shift Output Output Row Column Output Pin Address Address A21 Undefined A21 A20 Value A20 A19 A19 A18 A18 A17 A17 A16 A16 A15 A23 A15 ...
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For example, when MXC1 and MXC0 are set to 00 and an 8-bit shift is selected, the A23–A8 address bit values are output to pins A15–A0 the row address. The values for A21–A16 are undefined. The values of bits address ...
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CK A21–A0 RAS CAS WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.17 Short Pitch Access Timing Row address CDTY = Column address CDTY = 0 145 ...
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CK A21–A0 RAS CAS WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.18 Long Pitch Access Timing 8.5.3 Wait State Control Precharge State Control: When the microprocessor clock frequency is raised and the cycle period shortened, 1 cycle may ...
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A21–A0 RAS CAS Figure 8.19 Precharge Timing (Long Pitch) Control of Insertion of Wait States Using the WAIT Pin Input Signal: The number of wait states inserted into the DRAM access cycle can be controlled by ...
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Byte Access Control 16-bit width and 18-bit width DRAMs require different types of byte control signals for access. By setting the dual CAS signals/dual WE signals select bit (CW2) in DCR, the BSC allows selection of either the dual ...
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T CK A21–A0 RAS CASH Byte control CASL WRH WRL T CK A21–A0 RAS CASH CASL WRH Byte control WRL Figure 8.21 Byte Access Control Timing for DRAM Access (Upper Byte Write Cycle, Short Pitch Row address ...
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DRAM Burst Mode In addition to the normal mode of DRAM access, in which row addresses are output at every access and data then accessed (full access), the DRAM also has a high-speed page mode for use when continuously ...
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Short-Pitch, High-Speed Page Mode and Long-Pitch High-Speed Page Mode: When burst operation is selected by setting the BE bit DCR, short pitch high-speed page mode or long pitch high-speed page mode can be selected by setting the ...
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A21– A0 Row address RAS CAS WR AD15– A0 Note: Accesses A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces. Figure 8.24 Short-Pitch, High-Speed Page Mode (Write Cycle ...
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The high-level duty of the CAS signal can be selected in short-pitch, high-speed page mode using the CAS duty bit (CDTY) in DCR. When the CDTY bit is cleared to 0, the high-level duty is 50% of the T state; ...
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RAS Down Mode and RAS Up Mode: Sometimes access to another area can occur between accesses to the DRAM even though burst operation has been selected. Keeping the RAS signal low while this other access is occurring allows burst operation ...
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RAS up mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a DRAM access pauses for access to another space. Burst operation continues only while DRAM access is continuous. Figure 8.28 shows the ...
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When the clock is selected with the CKS2–CKS0 bits, RTCNT immediately begins to increment from its current value. This means that when the RTCOR cycle is set after the CKS2–CKS0 bits are set, the RTCNT count may already be higher ...
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Self-Refresh Mode: Some DRAMs have a self-refresh mode (battery back-up mode). This is a type of a standby mode in which the refresh timing and refresh addresses are generated inside the DRAM chip. When the RFSHE and RMODE bits in ...
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Table 8.11 Refresh and Bus Cycle Contention External Memory Space, Multiplexed I/O Space Type of Read Write Refresh Cycle Cycle CAS-before- Yes No RAS refresh Self-refresh Yes Yes Yes: Can be executed in parallel No: Cannot be executed in parallel ...
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Address/Data Multiplexed I/O Space Access The BSC is equipped with a function that multiplexes address and data input/output on pins AD15–AD0 in area 6. This allows the SH microprocessor to be directly connected to peripheral chips that require address/data ...
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A high-level duty of 35% or 50% can be selected for the RD signal using the RD duty bit (RDDTY) in BCR. When RDDTY is 1, the high-level duty is 35% of the state, lengthening the ...
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These types can be selected using the BAS bit in BCR. See section 8.4.3, Byte Access Control, for details. 8.7 Parity Check and Generation The BSC can check and generate parity for data input and output to ...
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Warp Mode In warp mode, an external write cycle or DMA single address mode transfer cycle and an internal access cycle (read/write to on-chip memory or on-chip supporting modules) operate independently and in parallel. Warp mode is entered by ...
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CK A21– A0 CSn External space write WR AD15– AD0 External space Internal address Internal On-chip write supporting strobe module write Internal data bus Internal On-chip read supporting strobe module read Internal data bus Figure 8.34 Warp Mode Timing (Access ...
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Table 8.12 Bus Cycle States when Accessing Address Spaces Address Space External memory (areas 1, 3– state fixed; WAIT signal External memory (Areas long wait avail-able) DRAM space (area 1) Multiplexed I/O space (area 6) ...