IS61SP6436-133TQ Integrated Silicon Solution, IS61SP6436-133TQ Datasheet

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IS61SP6436-133TQ

Manufacturer Part Number
IS61SP6436-133TQ
Description
64K x 36 synchronous pipelined static RAM
Manufacturer
Integrated Silicon Solution
Datasheet
IS61SP6436
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Pentium™ or linear burst sequence control
• Three chip enables for simple depth expansion
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
• Control pins mode upon power-up:
FAST ACCESS TIME
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.
We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
SR029-1C
08/11/99
IS61SP6436
64K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
Symbol
control
using MODE input
and address pipelining
eliminate multiple bank bus contention.
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or V
t
t
KQ
KC
CCQ
to alter their power-up state
Parameter
Clock Access Time
Cycle Time
Frequency
-133
Q
133
7.5
5
DESCRIPTION
The
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the i486™, Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 36 bits, fabricated with
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
DQ9-DQ16,
controls DQP4 and DQ25-DQ32, conditioned by
LOW. A LOW on
Bursts can be initiated with either
Processor) or
pins. Subsequent burst addresses can be generated inter-
nally by the IS61SP6436 and controlled by the
address advance) input pin.
Asynchronous signals include output enable (
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
(or no connect) on MODE pin selects INTERLEAVED Burst.
-117
117
8.5
ISSI
5
controls DQP1 and DQ1-DQ8,
IS61SP6436 is a high-speed, low-power synchro-
BW3
100
ADSC
10
-5
5
Q
, on MODE pin selects LINEAR Burst. A V
GW
controls DQP3 and DQ17-DQ24,
(Address Status Cache Controller) input
input would cause all bytes to be written.
12
83
-6
6
13
75
-7
7
BW2
ADSP
JULY 1999
15
66
-8
8
controls DQP2 and
ISSI
ISSI
(Address Status
OE
MHz
), sleep mode
Unit
's advanced
ns
ns
ADV
BWE
ISSI
(burst
being
BW4
CCQ
®
1
®

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IS61SP6436-133TQ Summary of contents

Page 1

... ADSC Processor) or (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated inter- nally by the IS61SP6436 and controlled by the address advance) input pin. Asynchronous signals include output enable ( input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. ...

Page 2

... IS61SP6436 BLOCK DIAGRAM CLK ADV ADSC ADSP 16 A15-A0 GW BWE BW4 BW3 BW2 BW1 CE CE2 CE2 OE 2 MODE A0' Q0 CLK A0 BINARY COUNTER A1 CLR ADDRESS REGISTER CE CLK DQP4 DQ32-DQ25 BYTE WRITE REGISTERS CLK D Q DQP3 DQ24-DQ17 BYTE WRITE ...

Page 3

... IS61SP6436 PIN CONFIGURATION 100-Pin TQFP and PQFP (Top View) 100 DQP3 2 DQ17 3 DQ18 4 VCCQ 5 GNDQ 6 DQ19 DQ20 7 8 DQ21 9 DQ22 10 GNDQ 11 VCCQ 12 DQ23 13 DQ24 VCCQ 14 15 VCC GND 18 DQ25 19 DQ26 ...

Page 4

... IS61SP6436 TRUTH TABLE Address Operation Used Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Begin Burst External ...

Page 5

... IS61SP6436 INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = GND A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) ...

Page 6

... IS61SP6436 OPERATING RANGE Range Ambient Temperature Commercial +70 C Industrial – + ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current LO POWER SUPPLY CHARACTERISTICS ...

Page 7

... IS61SP6436 (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions MHz, Vcc = 3.3V TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

Page 8

... IS61SP6436 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (1) Clock High to Output Invalid KQX (1,3) t Clock High to Output Low-Z KQLZ (1,3) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 9

... IS61SP6436 READ CYCLE TIMING t KC CLK ADSP t SS ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t KQ High-Z ...

Page 10

... IS61SP6436 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Address Setup Time AS t Address Status Setup Time SS t Write Setup Time WS t Data In Setup Time DS t Chip Enable Setup Time CES t Address Advance Setup Time ...

Page 11

... IS61SP6436 WRITE CYCLE TIMING t CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A15-A0 WR1 BWE t WS BW4-BW1 WR1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT ...

Page 12

... IS61SP6436 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (1) Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 13

... IS61SP6436 READ/WRITE CYCLE TIMING CLK ADSP t SS ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t KQ High-Z DATA ...

Page 14

... IS61SP6436 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (3) Clock High to Output Invalid KQX (3,4) t Clock High to Output Low-Z KQLZ (3,4) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 15

... IS61SP6436 SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 GW BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t High-Z DATA IN ZZ Single Read Integrated Silicon Solution, Inc ...

Page 16

... IS61SP6436 ORDERING INFORMATION Commercial Range +70 C Frequency (MHz) Industrial Range: – +85 C Frequency (MHz) 16 Order Part Number 133 IS61SP6436-133TQ IS61SP6436-133PQ 117 IS61SP6436-117TQ IS61SP6436-117PQ 100 IS61SP6436-5TQ IS61SP6436-5PQ 83 IS61SP6436-6TQ IS61SP6436-6PQ 75 IS61SP6436-7TQ IS61SP6436-7PQ 66 IS61SP6436-8TQ IS61SP6436-8PQ Order Part Number 117 IS61SP6436-117TQI IS61SP6436-117PQI 100 ...

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