IC41C16100S-50KG INTEGRATED CIRCUIT SOLUTION, IC41C16100S-50KG Datasheet

no-image

IC41C16100S-50KG

Manufacturer Part Number
IC41C16100S-50KG
Description
Manufacturer
INTEGRATED CIRCUIT SOLUTION
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IC41C16100S-50KG
Manufacturer:
ICSI
Quantity:
20 000
IC41C16100S
IC41LV16100S
Integrated Circuit Solution Inc.
DR010-0D 11/26/2004
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Document Title
1M x 16 bits Dynamic RAM with EDO Page Mode
Revision History
0A
0B
0C
0D
Revision No
History
Initial Draft
Revise for typographic
Add Pb-free package
Change t
COH
from 5ns to 4ns
Draft Date
June 5,2001
November 9,2001
May 06,2004
November 26,2004
Remark
1

Related parts for IC41C16100S-50KG

IC41C16100S-50KG Summary of contents

Page 1

... IC41C16100S IC41LV16100S Document Title bits Dynamic RAM with EDO Page Mode Revision History Revision No History 0A Initial Draft 0B Revise for typographic 0C Add Pb-free package 0D Change t COH The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products ...

Page 2

... EDO Page Mode. EDO Page Mode allows 1,024 ran- dom accesses within a single row with access cycle time as short per 16-bit word. The Byte Write control, of upper and lower byte, makes the IC41C16100S ideal for use in 16-, 32-bit wide data bus systems. These features make the IC41C16100Sand IC41LV16100S ...

Page 3

... IC41C16100S IC41LV16100S FUNCTIONAL BLOCK DIAGRAM OE WE CAS LCAS CLOCK UCAS GENERATOR RAS RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS A0-A9 Integrated Circuit Solution Inc. DR010-0D 11/26/2004 WE CONTROL CAS WE LOGICS DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY 1,048,576 CONTROL LOGIC I/O0-I/O15 ...

Page 4

... IC41C16100S IC41LV16100S TRUTH TABLE Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write (1,2) EDO Page-Mode Read (2) 1st Cycle: 2nd Cycle: Any Cycle: EDO Page-Mode Write ...

Page 5

... IC41C16100S IC41LV16100S Functional Description The IC41C16100S and IC41LV16100S is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9 time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS) ...

Page 6

... IC41C16100S IC41LV16100S ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Voltage on Any Pin Relative to GND T V Supply Voltage CC I Output Current OUT P Power Dissipation D T Commercial Operation Temperature A Industrial Operationg Temperature T Storage Temperature STG Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 7

... IC41C16100S IC41LV16100S ELECTRICAL CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current IO V Output High Voltage Level OH V Output Low Voltage Level OL I Standby Current: TTL Standby Current: CMOS Operating Current ...

Page 8

... IC41C16100S IC41LV16100S AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Random READ or WRITE Cycle Time RC t Access Time from RAS RAC t Access Time from CAS CAC t Access Time from Column-Address AA t RAS Pulse Width RAS t RAS Precharge Time RP t CAS Pulse Width ...

Page 9

... IC41C16100S IC41LV16100S AC CHARACTERISTICS (Continued) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Column-Address Setup Time to CAS ACH Precharge during WRITE Cycle t OE Hold Time from WE during OEH READ-MODIFY-WRITE cycle t Data-In Setup Time (15, 22 Data-In Hold Time (15, 22 READ-MODIFY-WRITE Cycle Time ...

Page 10

... IC41C16100S IC41LV16100S Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the (MIN) and V (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V ...

Page 11

... IC41C16100S IC41LV16100S READ CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE Note referenced from rising edge of RAS or CAS, whichever occurs last. OFF Integrated Circuit Solution Inc. DR010-0D 11/26/2004 RAS t CSH t RSH CAS CLCH RCD RAD RAL ...

Page 12

... IC41C16100S IC41LV16100S EARLY WRITE CYCLE (OE = DON'T CARE) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I RAS t CSH t RSH CAS CLCH RCD RAD RAL RAH ASC CAH t ACH Column t CWL t RWL t WCR t t WCS WCH DHR ...

Page 13

... IC41C16100S IC41LV16100S READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE Integrated Circuit Solution Inc. DR010-0D 11/26/2004 t RWC t RAS t CSH t t CAS RCD RAD RAH ASC CAH Column t RWD t t CWD RCS t AWD ...

Page 14

... IC41C16100S IC41LV16100S EDO-PAGE-MODE READ CYCLE RAS t CRP UCAS/LCAS t t ASR ADDRESS Row t RAH WE Open I/O OE Note can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both PC measurements must meet the t specifications RASP t CSH ...

Page 15

... IC41C16100S IC41LV16100S EDO-PAGE-MODE EARLY-WRITE CYCLE RAS t CRP UCAS/LCAS t t ASR ADDRESS Row t RAH WE I/O OE Integrated Circuit Solution Inc. DR010-0D 11/26/2004 t RASP t CSH CAS, RCD CP t CLCH ACH RAD ASC CAH ASC Column Column t CWL t WCS t t WCH ...

Page 16

... IC41C16100S IC41LV16100S EDO-PAGE-MODE READ-WRITE CYCLE RAS t CRP t RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RWD t RCS WE t RAC Open I/O OE Note can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both ...

Page 17

... IC41C16100S IC41LV16100S EDO-PAGE-MODE READ-EARLY-WRITE CYCLE RAS t t CRP RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RCS WE t RAC Open I/O OE Integrated Circuit Solution Inc. DR010-0D 11/26/2004 (Psuedo READ-MODIFY WRITE) t RASP t CSH CAS CP CAS CAH ASC ...

Page 18

... IC41C16100S IC41LV16100S AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS t CRP t RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RCS WE t RAC Open I/O OE RAS RAS RAS RAS-ONLY REFRESH CYCLE RAS RAS t CRP UCAS/LCAS t ASR ADDRESS I RASP t CSH t PC ...

Page 19

... IC41C16100S IC41LV16100S CBR CBR REFRESH CYCLE CBR CBR CBR (Addresses; WE DON'T CARE) RAS t RPC t CP UCAS/LCAS I/O HIDDEN REFRESH CYCLE (1) RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O OE Notes Hidden Refresh may also be performed after a Write Cycle. In this case LOW and OE = HIGH. ...

Page 20

... TSOP-2(Pb-free) IC41C16100S-60K(G) 400mil SOJ(Pb-free) IC41C16100S-60T(G) 400mil TSOP-2(Pb-free) Order Part No. Package IC41C16100S-45KI(G) 400mil SOJ(Pb-free) IC41C16100S-45TI(G) 400mil TSOP-2(Pb-free) IC41C16100S-50KI(G) 400mil SOJ(Pb-free) IC41C16100S-50TI(G) 400mil TSOP-2(Pb-free) IC41C16100S-60KI(G) 400mil SOJ(Pb-free) IC41C16100S-60TI(G) 400mil TSOP-2(Pb-free) Don’t Care Units ns ...

Page 21

... IC41C16100S IC41LV16100S ORDERING INFORMATION: 3.3V (Pb-free) Commercial Range: 0°C to 70°C Speed (ns ORDERING INFORMATION: 3.3V (Pb-free) Industrial Range: -40°C to 85°C Speed (ns NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, Integrated Circuit Solution Inc. DR010-0D 11/26/2004 Order Part No. Package IC41LV16100S-45K(G) 400mil SOJ(Pb-free) ...

Related keywords