R65C51P1 ETC, R65C51P1 Datasheet
R65C51P1
Available stocks
Related parts for R65C51P1
R65C51P1 Summary of contents
Page 1
DESCRIPTION The Rockwell CMOS R65C51 Asynchronous Interface Adapter (ACIA) provides an easily implemented, pro- gram controlled interface between 8-bit microprocessor-based systems and serial communication data sets and modems. The ACIA has an internal baud rate generator. This feature elim- inates ...
Page 2
RGSCEi’O RSl ------ $2 TIMING RES FUNCTIONAL DESCRIPTION : block diagram of the ACIA is presented in Figure 2 followed zy descrtption of each functional element of the device. a BUFFERS DATA BUS The interfaces the system data lines to ...
Page 3
R&C51 STATUS REGISTER The Status Register indicates the state of interrupt conditions and other non-interrupt status lines. The interrupt conditions are the Data Set Ready, Data Carrier Detect, Transmitter Data Reg- ister Empty and Receiver Data Register Full as reported ...
Page 4
R65C5 1 CONTROL REGISTER Y antrot selects the desired baud rate, frequency Register -. word length, and the number of stop bits S8R WL 1 RCS SBN ’ SBR3 SBR2 SBRl SBRO ...
Page 5
R65C51 COMMAND REGISTER The Command Register controls specific modes and functions. 76543210 TIC PMC PME REM 1 - IRD DTR TIC1 TIC0 PNCl PNCO Parity Mode Control (PMC) Bits 7 ‘i;j- 0 Odd parity transmitted/received 0 1 Even ...
Page 6
SIGNALS NTERFACE _ * srows the ACIA interface signals associated with the -&zrocessor and the modem. TRANSMIT cl DATA & SHIFT REGISTERS I/O BAUD CONTROL RATE GENERATOR 62 I COMMAND RES REGISTER Figure 4. ACIA Interface Diagram ICROPROCESSOR ...
Page 7
R65C51 ACIA/MODEM INTERFACE Crystal Pins (XTLI, XTLO) These pins are normally directly connected to the parallel mode external crystal (1.8432 MHz) to derive the various baud rates. Alternatively, an externally generated clock can drive the XTLI pin, in which case ...
Page 8
Data Receive 5,mliar to the Continuous Data Trasit Jperatlon of this mode is to assert IRQ when the ACIA has a full data word. This occurs at about --led :m Stop Bit. The processor must read the Status ...
Page 9
R65C5 1 on Transmitter Effect of CTS ?f% is the Clear-to-Send signal generated by the modem normally low (true state) but may go high in the event of some modem problems. When this occurs, the TxD line goes ...
Page 10
RfjSCS f - Ecno Mode Timing p 2_w a,!oce. the TxD line re-transmits the data on the RxD xoaved by ‘? of the bit time, as shown in Figure 10 CTS on Echo Mode Operation Effect ‘n Echo ...
Page 11
R65CSl Overrun in Echo Mode If Overrun occurs in Echo Mode, the Receiver is affected the same way as a normal overrun in Receive Mode. For the re- transmitted data, when overrun occurs, the TxD line goes to the \ ...
Page 12
Asynchronous Communications Interface Adapter (ACIA) fq6sCSf gmt of on Receiver -ccem output Indicating the status of the carrier-fre _;s;ec:.on clrcult of the modem -arr:er. Normally, when this occurs, the modem will .- c:ng ...
Page 13
R65C51 Transmit Continuous “BREAK” This mode is selected via the ACIA Command Register and causes the Transmitter to send continuous ters, beginning with the next character transmitted. At least one full “BREAK” character will be transmitted, even if the processor ...
Page 14
REGISTER OPERATION Z’ r-0 soecial of the various status bits, there funCtiOnS *- st;Sej:eo sequence for checking them. :“1 XIA should be interrogated, Lz_‘s. -’ ‘s Register za;c 5:&d _ ,-:era!:on automatically clears Bit 7 ...
Page 15
R65C51- Control Dlviaor Selected Regieter Bite Internel Counter Divisor Selected ...
Page 16
Asynchronous Communications Interface Adapter (ACIA) &@,osflC LOOP-BACK OPERATING MODES XK diagram for a system incorporating ii g-3 - =$Lre 18 cesiraole to include in the system a facility for “loop- .ss;,rg. =f which ...
Page 17
R65C51 READ TIMING DIAGRAM Timing diagrams for transmit with external clock, receive with external clock, and m generation are shown in Figures 20, 21 and 22, respectively. The corresponding are listed in Table 3. Table 3. Transmit/Receive Transmit/Receive 175 fcli ...
Page 18
CHARACTERISTICS parameter . Yme 22 :,c:e :2 -‘,.se .Vldth - a:,~ Time Set-Up :c:.5~s Aold Time a*,? +I-tip Time Time = a.5 -Oq 3~s Set-Up Time ~3~3 zala Hold Time 3~s aeac ’ Time (Valid Data) Access rold ...
Page 19
R65C51 ABSOLUTE MAXIMUM RATINGS’ OPERATING CONDITIONS DC CHARACTERISTICS (Vcc = 5.OV f5%, Vss = T”, unless otherwise noted) I Parameter I j Input High Voltage : Input Low Voltage ! Input Leakage ...