AM79Q021JC ETC-unknow, AM79Q021JC Datasheet
AM79Q021JC
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AM79Q021JC Summary of contents
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Am79Q02/021/031 Quad Subscriber Line Audio-Processing Circuit (QSLAC™) Devices DISTINCTIVE CHARACTERISTICS Performs the functions of four codec/filters Software programmable: — SLIC input impedance — Transhybrid balance — Transmit and receive gains — Equalization (frequency response) — Digital I/O pins ...
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TABLE OF CONTENTS Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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BLOCK DIAGRAM Analog VIN 1 Signal Processing Channel 1 (CH 1) VOUT 1 VIN 2 Signal Processing Channel 2 (CH 2) VOUT 2 VIN 3 Signal Processing Channel 3 (CH 3) VOUT 3 VIN4 Signal Processing Channel 4 (CH 4) ...
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ORDERING INFORMATION Standard Products Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79Q02/021/031 DEVICE NUMBER/DESCRIPTION Am79Q02/021/031 Quad Subscriber Line Audio-Processing Circuit (QSLAC) Device ...
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... VOUT 7 1 VIN 8 1 VOUT 9 2 VIN 10 2 VCCA 11 VREF 12 Am79Q021JC AGND 13 VIN 14 3 VOUT 15 3 VIN 16 4 VOUT Notes: 1. Pin 1 is marked for orientation. 2. RSVD = Reserved pin; should not be connected externally to any signal or supply. ...
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CONNECTION DIAGRAM (TQFP PACKAGE) Top View VOUT 1 VIN 1 VOUT 2 VIN 2 VCCA VREF AGND VIN 3 VOUT 3 VIN 4 VOUT 4 Notes: 1. Pin 1 is marked for orientation. 2. RSVD = Reserved pin; should not ...
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PIN DESCRIPTIONS Pin Names Type CD1 –CD1 , Inputs/Outputs Control and Data. CD1 and CD2 are TTL compatible programmable Input or Output (I/ CD2 –CD2 ports. They can be used to monitor or control the state of SLIC ...
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Pin Names Type DCLK Input Data Clock. The Data Clock input shifts data into and out of the microprocessor interface of the QSLAC device. The maximum clock rate is 4.096 MHz. DIO Input/Output Data. Control data is serially written into ...
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Pin Names Type VOUT – Outputs Analog. The received digital data at DRA or DRB is processed and converted to an analog 1 VOUT signal at the VOUT pin. VOUT 4 2, VOUT voltages are referenced to VREF. VREF Output ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . –60°C < T Ambient Operating Temperature –40°C < T Ambient Relative Humidity . . . . . . . . . . . . 5% to 95% ...
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ELECTRICAL CHARACTERISTICS Typical values are for ° C and nominal supply voltages. Minimum and maximum values are over the A temperature and supply voltage ranges shown in Operating Ranges. Symbol Parameter Descriptions V Input Low voltage IL ...
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Transmission Characteristics Table 1. 0 dBm0 Voltage Definitions with Unity Gain GX, GR, AX, and AR Signal at Digital Interface A-law digital mW or equivalent (0 dBm0) µ-law digital mW or equivalent (0 dBm0) ±22,827 peak linear ...
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Attenuation Distortion ...
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Variation of Gain with Input Level The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 3 for either transmission path when the input is a sine wave signal of frequency 1014 Hz. ...
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Total Distortion, Including Quantizing Distortion The signal-to-total distortion will exceed the limits shown in Figure 4 for either transmission path when the input is a sine wave signal of frequency 1014 Hz ...
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Discrimination against Out-of-Band Input Signals When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be frequency components below 4 kHz at the digital output which are caused by the out-of-band ...
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Discrimination against 12- and 16-kHz Metering Signals If the QSLAC device is used in a metering application where 12-kHz or 16-kHz tone bursts are injected onto the telephone line toward the subscriber, a portion of those tones may also appear ...
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Overload Compression Figure 7 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The conditions for this figure are: (1) 1.2 dB < GX ≤ 12 dB; (2) –12 dB ≤ GR ...
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SWITCHING CHARACTERISTICS over operating range (unless otherwise noted) Min and max values are valid for all digital outputs with a 150 pF load, except CD1–C5 with load. Microprocessor Interface No. Symbol 1 t Data clock period DCY ...
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Master Clock No. Symbol 37 A Master clock accuracy MCY 38 t Rise time of clock MCR 39 t Fall time of clock MCF 40 t MCLK High pulse width MCH 41 t MCLK Low pulse width MCL Auxiliary Output ...
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Microprocessor Interface (Input Mode DCLK Data D I/O Valid Outputs C5–C1 Microprocessor Interface (Output Mode DCLK Three-State V Data OH ...
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PCM Highway Timing for (Transmit on Negative PCLK Edge PCLK TSCA/ TSCB 32 DXA/DXB DRA/DRB Time Slot Zero Clock Slot Zero ...
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PCM Highway Timing for (Transmit on Positive PCLK Edge PCLK TSCA/ TSCB DXA/DXB DRA/DRB 24 Time Slot Zero Clock Slot Zero ...
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OPERATING THE QSLAC DEVICE The following sections describe the operation of the four independent channels of the QSLAC device. The des cr i pti hann ...
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Assigner E1 Multiplex Operation The QSLAC device can multiplex input data from the CD1 SLIC I/O pin into two separate status bits per channel (CD1 and CD1B bits in the SLIC Input/Output register, Commands 52/53h, and CDA and CDB ...
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Therefore, during this multiplexing, the CD1 bit always has loop-detect status and the CD1B bit always has ground-key detect status ...
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CD1 CD2 I/O Direction Register MPI Command 22 Output Latch SLIC Output Data Register MPI Command 20 EE1 Bit E1 Source (Internal) Delay See Figure 10 MCLK/E1 for details E1P INT Note: * Transparent latches: When enable ...
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E1 GK Enable LD Enable DET Output from SLIC (CD1 Pin Input) Contains CD1 Pin Valid LD Input Data Status CD1 Tracks Register DET State Operation CD1B Register Operation Debounce Filters Operation Each channel is equipped with two debounce filter ...
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CD1 kHz) Notes: * Transparent latch: Output follows input when EN is high; output holds last state when EN is low Debounce Counter: Output goes high after counting to programmed (DSH) number of 1 ...
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Real-Time Data Register Operation To obtain time-critical data such as off/on-hook and ring trip information from the SLIC with a minimum of processor time and effort, the QSLAC device contains an 8-bit Real Time Data register. This register contains CDA ...
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Transmit time slots and receive time slots are set and 3 for channels and 4, respectively. The clock slots are set to 0, with transmit on the negative edge. 8. DXA port ...
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Two-Wire Impedance Matching Two feedback paths on the QSLAC device synthesize the two-wire input impedance of the SLIC by providing a programmable feedback path from VIN to VOUT. The Analog Impedance Scaling Network (AISN programmable analog gain of ...
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TSC output turned on. For example, if the PCLK frequency is 1.544 MHz ( and the transmit clock slot is ...
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During this test, the VIN input is ignored and the VOUT output is connected to VREF. Speech Coding The A/D and D/A conversion follows either the A-law µ ...
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PCLK FS Normal Frame (Not Robbed-Bit) PCLK FS Robbed-Bit Frame Figure 13. Robbed-Bit Frame Default Filter Coefficients The QSLAC device contains an internal set of default coefficients for the programmable filters. These coeffi- cients were determined to allow reasonable system ...
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Commands are provided to assign values to the following global chip parameters: Transmit PCM Clock Edge Interrupt Output Drive state Chopper Clock Frequency Select Signaling on the PCM Highway Select Master Clock Frequency Channel Enable register Debounce Time for CD1 ...
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SUMMARY OF MPI COMMANDS* Number 6,7 8,9 10,11 12,13 14, 18,19 20,21 22,23 24,25 26,27 28,29 30 31,32 33,34 35,36 37, 38 39, 40 41, 42 43 48, 49 ...
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MPI COMMAND STRUCTURE This section details each MPI command. Each command is shown along with the format of any additional data bytes that follow. For details of the filter coefficients of the form C section on page 56. Unused bits ...
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No Operation (06h) Command 5. Activate Channel (Operational Mode) (0Eh) Command This command places the device in the Active mode and sets CSTAT = 1. No valid PCM data is transmitted until after the second FS pulse is received ...
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Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge (44/45h) R Write R Read Command I/O Data Transmit on A and B TAB = 0* TAB = 1 Transmit Edge XE = ...
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Master Clock Frequency CSEL = 0000 CSEL = 0001 CSEL = 0010 CSEL = 0011 CSEL = 01xx CSEL = 10xx CSEL = 11xx CSEL = 1010* These commands do not depend on the state of the Channel Enable Register. ...
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Read Real-Time Data Register (4D/4Fh not clear interrupt Clear interrupt This register writes/reads real-time data with or without clearing the interrupt. Command Output Data Real Time Data CDA1 CDB1 CDA2 CDB2 ...
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Write/Read SLIC Input/Output Register (52/53h) R Write R Read Command I/O Data RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Pins CD1, CD2, and C3 through ...
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Write/Read Operating Functions (60/61h) R Write R Read Command I/O Data Linear Code C C A-law or µ-law A/µ A/µ Filter EGR = 0* EGR ...
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Write/Read Interrupt Mask Register (6C/6Dh) R Write R Read Command I/O Data Mask CD Interrupt MCDxy = 0 MCDxy = Masked: A change does not cause the Interrupt Pin to go ...
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Read Revision Code Number (RCN) (73h) Command I/O Data This command returns an 8-bit number (RCN) describing the revision number of the QSLAC device. This command does not depend on the state of the Channel Enable Register. 31, 32. ...
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Write/Read Z Filter Coefficients (FIR and IIR) (84/85h) R Write R Read This command writes and reads both the FIR and IIR filter sections simultaneously. Command I/O Data Byte 1 I/O Data Byte 2 ...
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Write/Read B1 Filter Coefficients (86/87h) R Write R Read Command I/O Input Data Byte 1 I/O Input Data Byte 2 I/O Input Data Byte 3 I/O Input Data Byte 4 I/O Input Data Byte ...
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Write/Read X Filter Coefficients (88/89h) R Write R Read Command I/O Input Data Byte 1 I/O Input Data Byte 2 I/O Input Data Byte 3 I/O Input Data Byte 4 I/O Input Data Byte ...
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Write/Read R Filter Coefficients (8A/8Bh) R Write R Read Command I/O Input Data Byte 1 I/O Input Data Byte 2 I/O Input Data Byte 3 I/O Input Data Byte 4 I/O Input Data Byte ...
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Write/Read B2 Filter Coefficients (IIR) (96/97h) R Write R Read Command I/O Data Byte 1 I/O Data Byte 2 This function is described in Write/Read B1 Filter Coefficients (FIR) on page 49. Power Up ...
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Read Transmit PCM Data (CDh) Command Output Data Byte 1 Output Data Byte 2 RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Upper Transmit Data XDAT contains A-law or µ -law ...
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Write/Read IIR Z Filter Coefficients (IIR only) (9A/9Bh) R Write R Read This command writes/reads the IIR filter section only, without affecting the FIR. Command I/O Data Byte 11 I/O Data Byte 12 I/O ...
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Write/Read Ground Key Filter (E8/E9h) R Write R Read Command I/O Data Filter Ground Key GK = 0–15 GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or ...
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PROGRAMMABLE FILTERS General Description of CSD Coefficients The filter functions are performed by a series of multiplications and accumulations. A multiplication occurs by repeatedly shifting the multiplicand and summing the result with the previous value at that summation node. The ...
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In the QSLAC device, a coefficient, h coefficients, each being made bits and formatted as Cxy mxy, where Cxy is 1 bit (MSB) and mxy is 3 bits. Each CSD coefficient is broken down as follows: Cxy ...
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A-Law and µ-Law Companding Table 2 and Table 3 show the companding definitions used for A-law and µ -law PCM encoding Intervals Value at Segment x Interval Segment Number Size End Points 128 6 ...
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Intervals Value at Segment x Interval Segment Number Size End Points 256 128 ...
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APPLICATIONS The QSLAC device performs a programmable codec/ filter function for four telephone lines. It interfaces to the telephone lines through an Legerity SLIC device or a transformer with external buffering. The QSLAC device provides latched digital I/O to control ...
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PHYSICAL DIMENSIONS PL032 SLAC Products Dwg rev AH; 10/99 61 ...
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PL044 62 Am79Q02/021/031 Data Sheet Dwg rev. AN; 8/99 ...
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PQT044 SLAC Products Dwg rev AS; 08/99 63 ...
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... REVISION SUMMARY Revision B to Revision C • In the Connection Diagrams section, “INT” was changed to “INT” for Am79Q021JC and Am79Q021VC. • “Frame sync” information was added to the first paragraph on page 31. Revision C to Revision D • Minor changes were made to the data sheet style and format to conform to Legerity standards. ...
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Notes: www.legerity.com ...
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Legerity provides silicon solutions that enhance the performance, speeds time-to-market, and lowers the system cost of our customers' products. By combining process, design, systems architecture, and a complete set of software and hardware support tools with unparalleled factory and worldwide ...
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The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with re- spect to the accuracy or completeness of the contents of this publication and reserves the right to make changes ...
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