KM416S1120DT-G8 ETC-unknow, KM416S1120DT-G8 Datasheet
KM416S1120DT-G8
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KM416S1120DT-G8 Summary of contents
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KM416S1120D SDRAM 512K x 16bit x 2 Banks Samsung Electronics reserves the right to change products or specification without notice. Synchronous DRAM LVTTL Revision 1.4 June 1999 - 1 - CMOS SDRAM Rev. 1.4 (Jun. 1999) ...
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... Modified power-up sequence. • Changed I from +/- 1uA to +/-10uA. LI • Changed tSAC and tSHZ of KM416S1120DT-G/F8@CL2 and KM416S1120DT-G/F10@CL3 from 7ns to 6ns. Revision 1.2 (March 1999) • Removed KM416S1120D-Z (125MHz @ CL2) part. • Supported tRDL=2CLK for -6 part which is distinguished by bucket code "J" . ...
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... ORDERING INFORMATION Part NO. KM416S1120DT-G/FC KM416S1120DT-G/F6 KM416S1120DT-G/F7 KM416S1120DT-G/F8 KM416S1120DT-G/F10 Data Input Register 512K x 16 512K x 16 Column Decoder Latency & Burst Length Programming Register LWE LCAS ...
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KM416S1120D PIN CONFIGURATION (TOP VIEW) A10/AP PIN FUNCTION DESCRIPTION Pin Name CLK System Clock CS Chip Select CKE Clock Enable /AP Address Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE ...
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KM416S1120D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. ...
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... I CC6 Note : 1. Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. KM416S1120DT-G** 5. KM416S1120DT-F Test Condition Burst Length = (min) ...
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KM416S1120D AC OPERATING TEST CONDITIONS Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200 Output 50pF 870 (Fig Output Load Circuit Note : ...
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KM416S1120D Parameter CLK cycle time Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address ...
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KM416S1120D SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge ...
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KM416S1120D MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA A /AP 10 Function RFU RFU W.B.L Test Mode A A Type Mode Register Set 0 1 Reserved 1 0 Reserved 1 ...
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KM416S1120D BURST SEQUENCE (BURST LENGTH = 4) Initial Address BURST SEQUENCE (BURST LENGTH = 8) Initial Address ...
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KM416S1120D DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V ...
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KM416S1120D DEVICE OPERATIONS (Continued) MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make ...
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KM416S1120D DEVICE OPERATIONS (Continued) DQM OPERATION The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero ...
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KM416S1120D BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4) CLK CMD WR CKE Internal CKE DQ(CL2 DQ(CL3 Not Written 2. DQM Operation 1) Write Mask (BL=4) ...
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KM416S1120D 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2 DQ(CL3) tCCD Note 2 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD Note 2 ...
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KM416S1120D 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2 DQ(CL3) tCCD Note 2 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD Note 2 ...
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KM416S1120D ( Continued ) (b) CL=3, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ RD iii) CMD DQM DQ RD iii) CMD DQM DQ iv) CMD RD DQM DQ 5. Write Interrupted by Precharge & DQM ...
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KM416S1120D 6. Precharge 1) Normal Write (BL=4) CLK WR CMD Normal Read (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 7. Auto Precharge 1) Normal Write (BL=4) CLK WR CMD ...
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KM416S1120D 8. Burst Stop & Interrupted by Precharge 1) Normal Write (BL=4) CLK CMD WR DQM Read Interrupted by Precharge (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 9. MRS 1) Mode Register Set CLK Note ...
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KM416S1120D 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal Note 1 CLK CMD 11. Auto Refresh & Self Refresh 1) Auto Refresh & Self Refresh Note 3 CLK Note 4 ...
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KM416S1120D 12. About Burst Type Control Sequential Counting Basic MODE Interleave Counting Random Random column Access MODE CLK CCD 13. About Burst Length Control 1 2 Basic MODE 4 8 Full Page Special BRSW MODE Random Burst ...
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KM416S1120D FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State IDLE ...
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KM416S1120D FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State Row Activating ...
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KM416S1120D FUNCTION TRUTH TABLE (TABLE 2) CKE Current CKE CS n State (n- Self Refresh ...
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KM416S1120D Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 tCH CLOCK tCC CKE *Note 1 CS tRCD tSH RAS tSS tSH CAS tSS tSH ADDR Ra Ca tSS *Note 2 *Note 2 ...
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KM416S1120D *Note : 1. All inputs expect CKE & DQM can be don 2. Bank active & read/write are controlled by BA Enable and disable auto precharge function are controlled by ...
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KM416S1120D Power Up Sequence CLOCK CKE High level is necessary CS tRP RAS CAS ADDR BA A /AP 10 High DQM High level is necessary Precharge Auto Refresh (All Banks ...
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KM416S1120D Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS tRCD RAS CAS ADDR Ra Ca0 CL=2 tRAC *Note 3 CL=3 tRAC *Note 3 WE DQM ...
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KM416S1120D Page Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS tRCD RAS CAS ADDR Ra Ca0 CL=2 CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) ...
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KM416S1120D Page Read Cycle at Different Bank @Burst Length CLOCK CKE *Note 1 CS RAS CAS RAa CAa RBb ADDR BA A /AP RAa RBb 10 DQ CL=2 CL=3 WE DQM Row Active Row Active ...
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KM416S1120D Page Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS ADDR RAa CAa BA A /AP RAa 10 DQ DAa0 DAa1 DAa2 WE DQM Row Active Row Active (A-Bank) Write (A-Bank) ...
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KM416S1120D Read & Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS RAa CAa ADDR BA A /AP RAa 10 DQ CL=2 CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : ...
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KM416S1120D Read & Write Cycle with Auto Precharge I @Burst Length CLOCK CKE CS RAS CAS ADDR / CL=2 CL=3 WE DQM Read with Row Active Auto ...
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KM416S1120D Read & Write Cycle with Auto Precharge II @Burst Length CLOCK CKE CS RAS CAS ADDR / CL=2 CL=3 WE DQM Row Active Auto Precharge (A-Bank) *Note : ...
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KM416S1120D Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length CLOCK CKE CS RAS CAS ADDR / DQM Row Active Read *Note : 1. DQM is ...
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KM416S1120D Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page CLOCK CKE CS RAS CAS RAa CAa ADDR BA A /AP RAa 10 DQ CL=2 CL=3 WE DQM Row Active Read ...
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KM416S1120D Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page CLOCK CKE CS RAS CAS ADDR RAa CAa BA RAa A / DAa0 DAa1 DAa2 DAa3 DAa4 WE ...
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KM416S1120D Burst Read Single bit Write Cycle @Burst Length CLOCK *Note 1 CKE CS RAS CAS ADDR RAa CAa BA A /AP RAa 10 DQ CL=2 DAa0 CL=3 DAa0 WE DQM Row Active Row Active ...
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KM416S1120D Active/Precharge Power Down Mode @CAS Latency=2, Burst Length CLOCK tSS *Note 1 CKE *Note 3 CS RAS CAS ADDR DQM Precharge Power-down Entry *Note : 1. Both banks ...
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KM416S1120D Self Refresh Entry & Exit Cycle CLOCK *Note 2 *Note 1 CKE tSS CS RAS CAS ADDR BA A / DQM Self Refresh Entry *Note : TO ENTER SELF REFRESH ...
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KM416S1120D Mode Register Set Cycle CLOCK HIGH CKE CS *Note 2 RAS *Note 1 CAS *Note 3 ADDR Key Ra DQ Hi-Z WE DQM MRS New Command * Both banks precharge should be completed before ...
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KM416S1120D PACKAGE DIMENSIONS 50-TSOP2-400CF #50 #1 0.10MAX [ ] 0.075MAX +0.10 (0.875) 0.30 -0.05 #26 #25 20.95 0.10 0.80TYP +0.10 [0.80 0.08] 0.05MIN 0.35 -0. CMOS SDRAM Unit : Millimeters 0~8 0.25 TYP +0.075 0.125 -0.035 1.20MAX 1.00 ...