RTL8110SB ETC-unknow, RTL8110SB Datasheet
RTL8110SB
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RTL8110SB Summary of contents
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... RTL8110SB(L) INTEGRATED GIGABIT ETHERNET CONTROLLER (LOM) DATASHEET Rev. 1.4 10 August 2004 Track ID: JATR-1076-21 ...
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... USING THIS DOCUMENT This document is intended for use by the software engineer when programming for Realtek RTL8110SB(L) controller chips. Information pertaining to the hardware design of products using these chips is contained in a separate document. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide ...
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... PCI B I ..................................................................................................................................................10 US NTERFACE 6.1.1. Byte Ordering .......................................................................................................................................................10 6.1.2. Interrupt Control .................................................................................................................................................. 11 6.1.3. Latency Timer ....................................................................................................................................................... 11 6.1.4. 64-Bit Addressing ................................................................................................................................................. 11 6.2. PCI B O ..................................................................................................................................................12 US PERATION 6.2.1. Target Read...........................................................................................................................................................12 6.2.2. Target Write ..........................................................................................................................................................13 6.2.3. Master Read .........................................................................................................................................................14 6.2.4. Master Write .........................................................................................................................................................15 6.2.5. Configuration Access............................................................................................................................................16 Integrated Gigabit Ethernet Controller (LOM) Table of Contents ...............................................................................................................................4 SOLATION ............................................................................................................................................7 ..........................................................................................................................................8 ........................................................................................................................................9 INS iii RTL8110SB(L) Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... MECHANICAL DIMENSIONS .......................................................................................................................................39 8.1. 128-P QFP M IN ECHANICAL 8.2. N 128-P QFP D OTES FOR IN 8.3. 128-P LQFP M IN ECHANICAL 8.4. N 128-P LQFP D OTES FOR IN 9. ORDERING INFORMATION..........................................................................................................................................43 Integrated Gigabit Ethernet Controller (LOM) .................................................................................................................................26 ATINGS C .................................................................................................................26 ONDITIONS ..........................................................................................................................................26 .....................................................................................................................................27 .....................................................................................................................................29 D ..................................................................................................................39 IMENSIONS ......................................................................................................................40 IMENSIONS D ................................................................................................................41 IMENSIONS ....................................................................................................................42 IMENSIONS iv RTL8110SB(L) Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... T 18 ABLE EASUREMENT ONDITION T 19 ABLE LOCK AND ESET PECIFICATIONS T 20 ABLE RDERING NFORMATION Integrated Gigabit Ethernet Controller (LOM) List of Tables ..............................................................................................................................4 SOLATION ............................................................................................................................................7 .........................................................................................................................................8 .......................................................................................................................................9 INS ................................................................................................................................26 ATINGS C .................................................................................................................26 ONDITIONS .........................................................................................................................................26 ....................................................................................................................................27 ..............................................................................................................................................27 P .................................................................................................................28 ARAMETERS .................................................................................................................................29 P ................................................................................................................30 ARAMETERS ..........................................................................................................................31 ..........................................................................................................................................43 v RTL8110SB(L) Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... BOVE Integrated Gigabit Ethernet Controller (LOM) List of Figures ...........................................................................................................................3 SSIGNMENTS O .............................................................................................................................10 RDERING ..................................................................................................................................11 .......................................................................................................................................12 .....................................................................................................................................13 ......................................................................................................................................14 .....................................................................................................................................15 T .....................................................................................................................28 IMING C .........................................................................................................30 ONDITIONS C ............................................................................................................30 ONDITIONS .........................................................................................................................................31 ...........................................................................................................................................31 ............................................................................................................................................33 ...........................................................................................................................................33 4GB ...................................................................................................................................34 4GB ................................................................................................................................. ....................................................................................................35 ISCONNECT - A .............................................................................................................36 BORT - A .............................................................................................................36 BORT E ......................................................................................................................37 NE XAMPLE 4GB (DAC) .......................................................................................................................38 4GB (DAC)......................................................................................................................38 vi RTL8110SB(L) Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when receiving. To better qualify for server use, the RTL8110SB(L) support the PCI Dual Address Cycle (DAC) command when the assigned buffers reside at a physical memory address higher than 4 Gigabytes ...
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... Encoding Supports IEEE 802.1Q VLAN tagging Serial EEPROM 3.3V signaling, 5V PCI I/O tolerant Transmit/Receive FIFO (8K/64K) support Supports power down/link down power saving Supports PCI Message Signaled Interrupt (MSI) 128-pin QFP package (RTL8110SB) and 128-pin LQFP package (RTL8110SBL) 2 Track ID: JATR-1076-21 RTL8110SB(L) Datasheet Rev. 1.4 ...
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... NC 75 SERRB PAR 76 77 CBEB1 78 VDD12 79 PCIAD15 80 GND VSSPST 81 82 PCIAD14 PCIAD13 83 Integrated Gigabit Ethernet Controller (LOM) RTL8110SB(L) Figure 1. 128-Pin (L)QFP Pin Assignments 3 RTL8110SB(L) Datasheet 19 MDI3- MDI3 VSS AVDDL 16 15 MDI2- 14 MDI2+ 13 VSS AVDDH 12 11 VSS 10 AVDDH 9 VSS CTRL25 8 ...
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... Isolate Pin: Active low. Used to isolate the RTL8110SB(L) from the PCI bus. The RTL8110SB(L) will not drive its PCI outputs (excluding PME#) and will not sample its PCI input (including PCIRSTB and PCICLK) as long as the Isolate pin is asserted. ...
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... As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. 29 Grant: This signal is asserted low to indicate to the RTL8110SB(L) that the central arbiter has granted the ownership of the bus to the RTL8110SB(L). This input is used when the device is acting as a bus master. ...
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... Integrated Gigabit Ethernet Controller (LOM) Pin No Description 30 Request: The RTL8110SB(L) will assert this signal low to request the ownership of the bus from the central arbiter. 46 Initialization Device Select: This pin allows the device to identify when configuration read/write transactions are intended for it. ...
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... AUX: Input pin to detect if Aux. Power exists or not on initial power-on. This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to aux. power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8110SB(L) assumes that no Aux. Power exists. 108 Input from serial data output pin of EEPROM ...
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... Regulator Control. Voltage control to external 1.2V regulator. Reference. External Resistor Reference. Table 7. LEDs Description LEDS1-0 00 LED0 Tx/Rx ACT(Tx/Rx) LINK10/100/ LED1 LINK100 1000 LED2 LINK10 FULL LED3 LINK1000 8 RTL8110SB( LINK10/ Tx ACT LINK10/100 LINK100/ /1000 ACT Rx FULL LINK1000/ - FULL ACT Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... Integrated Gigabit Ethernet Controller (LOM) Table 8. Power & Ground Pin No Description 126 Analog 1.2V power supply. Digital 1.2V power supply. 116 Digital 3.3V power supply. Digital Ground. Analog 2.5V power supply. Analog 3.3V power supply. Analog Ground. Table 9. NC (Not Connected) Pins Description Not Connected. 9 RTL8110SB(L) Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... ENDIAN bit of the C+ Command Register. When the RTL8110SB(L) is configured in big-endian mode, all the data in the data phase of either memory or I/O transaction to or from the RTL8110SB( big-endian mode. All data in the data phase of any PCI configuration transaction to RTL8110SB(L) should be little-endian, no matter whether the RTL8110SB(L) is set to big-endian or little-endian mode ...
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... Once the device gains control of the bus and issues FRAMEB, the Latency Timer will begin counting down. The LTR register specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8110SB(L). When the RTL8110SB(L) asserts FRAMEB, it enables its latency timer to count. If the RTL8110SB(L) deasserts FRAMEB prior to count expiration, the content of the latency timer is ignored. ...
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... IRDYB is asserted at that time, TRDYB will be forced HIGH on the next clock for 1 cycle, and then tri-stated. If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8110SB(L) will still make data available as described above, but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. ...
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... TRDYB will be forced HIGH for 1 cycle and then tri-stated. Target write operations must be 32-bits wide. If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8110SB(L) will still latch the first double word as described above, but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB ...
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... Master Read A Master Read operation starts with the RTL8110SB(L) asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB, Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3 cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB. ...
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... Master Write A Master Write operation starts with the RTL8110SB(L) asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB, Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3 cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB. ...
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... For the system to initiate a Configuration access, it must also generate IDSEL as well as the correct Command (1010b or 1011b) during the Address phase. The RTL8110SB(L) will respond as it does during Target operations. Configuration reads must be 32-bits wide, but writes may access individual bytes. ...
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... Rx LED In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring. Integrated Gigabit Ethernet Controller (LOM) Power On LED = High No Receiving Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Figure 8. Rx LED 17 RTL8110SB(L) Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Tx LED In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. Integrated Gigabit Ethernet Controller (LOM) Power On LED = High No Transmitting Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Figure 9. Tx LED 18 RTL8110SB(L) Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Tx/Rx LED In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring. Integrated Gigabit Ethernet Controller (LOM) Power On LED = High Tx/Rx Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Figure 10. Tx/Rx LED 19 RTL8110SB(L) Datasheet No Track ID: JATR-1076-21 Rev. 1.4 ...
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... LINK/ACT LED In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8110SB(L) is linked and operating properly. When this LED is high for extended periods, it indicates that a link problem exists. Integrated Gigabit Ethernet Controller (LOM) Power On LED = High No Link? Yes LED = Low No Tx/Rx packet? ...
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... NRZ and NRZI signals. After that, the NRZI signal is passed to the MLT-3 encoder, then to the DAC converter for transmission onto the media. In 1000Mbps mode, the RTL8110SB(L)’s PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continuous code-groups through 4D-PAM5 coding technology. ...
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... EEPROM, the 93C66 is a 4K-bit EEPROM). The EEPROM interface provides the ability for the RTL8110SB(L) to read from and write data to an external serial EEPROM device. Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be overridden following a power-on or software EEPROM auto-load command ...
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... Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held. • After restoration state, the RTL8110SB(L) transfers data that was not moved into the Tx FIFO buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted ...
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... The PMEn bit (CONFIG1#0) is set to 1. • The 16-bit CRC* of the received Wakeup Frame matches the 16-bit CRC* of the sample Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8110SB(L) is configured to allow direct packet wakeup, e.g. a broadcast, multicast, or unicast network packet. ...
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... The PMEn bit (bit0, CONFIG1) is set to 1. • The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1. • The RTL8110SB(L) may assert PME# in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space. ...
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... Integrated Gigabit Ethernet Controller (LOM) Table 11. Absolute Maximum Ratings Minimum -0.5 -0.5 -0.5 -0.5 -0.5 -55 Table 12. Recommended Operating Conditions Pins Minimum VDD33, 3.0 AVDDH AVDDL 2.32 VDD12, 1.13 VDD12A 0 Table 13. Crystal Requirements Description/Condition =25° RTL8110SB(L) Maximum 4 3 1.5 VDD33 + 0.5 VDD33 + 0.5 +125 Typical Maximum 3.3 3.6 2.5 2.67 1.2 1.28 70 125 Minimum Typical Maximum 25 -50 +50 -30 +30 ...
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... Integrated Gigabit Ethernet Controller (LOM) Description/Condition Table 14. Thermal Characteristics Minimum -55 0 Table 15. DC Characteristics Conditions Minimum 3.0 2.32 1. -8mA 0.9 * VDD33 8mA 0.5 * VDD33 -0 VDD33 or -1.0 GND V out = VDD33 -10 or GND 27 RTL8110SB(L) Minimum Typical Maximum 0.5 Maximum Units °C +125 °C 70 Typical Maximum 3.3 3.6 2.5 2.67 1.2 1.28 VDD33 ...
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... tsk tskh tskl tdih tdos STATUS VALID Figure 12. Serial EEPROM Interface Timing Table 16. EEPROM Access Timing Parameters EEPROM Type 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 28 RTL8110SB( tcs ... D0 BUSY twp tcsh tdoh Min. Max. 1000/250 10/10 4/1 1000/500 1000/250 Track ID: JATR-1076-21 ...
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... EEPROM Type 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 Table 17. PCI Bus Timing Parameters 66MHz Min Max 100 40 2^ RTL8110SB(L) Datasheet Min. Max. Unit 200/50 ns 0/0 ns 400/50 ns 400/100 ns 2000/500 ns 2000/500 ns 1000/500 ns 33MHz Min Symbol Parameter ...
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... V_trise, V_tfall V_test V_test T_on T_off T_su V_th V_test inputs valid V_tl Table 18. Measurement Condition Parameters Level 0.6Vcc 0.2Vcc 0.4Vcc 0.285Vcc 0.615Vcc 0.4Vcc 1 30 RTL8110SB(L) V_th V_tl V_th V_test V_tl T_h V_test V_max Units V/ns Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... Figure 15. 3.3V Clock Waveform T_skew V_ih T_skew V_il Figure 16. Clock Skew Diagram Table 19. Clock and Reset Specifications 66MHz Min Max 1 RTL8110SB(L) 0.4Vcc, peak-to-peak (minimum) V_test T_skew V_test 33MHz Min Symbol Parameter 30 ∞ mV/ns 2 Track ID: JATR-1076-21 ...
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... BUS CMD IRDYB TRDYB DEVSELB CLK 1 FRAMEB AD31-0 ADDRESS C/BE3-0B BUS CMD IRDYB TRDYB DEVSELB Integrated Gigabit Ethernet Controller (LOM DATA BE3-0B Figure 17. I/O Read DATA BE3-0B Figure 18. I/O Write 32 RTL8110SB( Track ID: JATR-1076-21 Datasheet 10 10 Rev. 1.4 ...
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... IDSEL AD31-0 C/BE3-0B IRDYB TRDYB DEVSELB Integrated Gigabit Ethernet Controller (LOM ADDRESS DATA BUS CMD BE3-0B Figure 19. Configuration Read ADDRESS DATA BUS CMD BE3-0B Figure 20. Configuration Write 33 RTL8110SB( Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... C/BE3-0B IRDYB TRDYB DEVSELB Integrated Gigabit Ethernet Controller (LOM ADDRESS DATA ADDRESS Figure 21. Bus Arbitration DATA-1 ADDRESS BUS CMD BE3-0B Figure 22. Memory Read Below 4GB 34 RTL8110SB( DATA DATA-2 DATA-3 Track ID: JATR-1076-21 Datasheet 10 9 Rev. 1.4 ...
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... IRDYB TRDYB STOPB DEVSELB Figure 24. Target Initiated Termination - Disconnect Integrated Gigabit Ethernet Controller (LOM ADDRESS DATA-1 DATA-2 BUS CMD BE3-0B-1 BE3-0B-2 Figure 23. Memory Write Below 4GB RTL8110SB(L) Datasheet DATA-3 BE3-0B Track ID: JATR-1076-21 Rev. 1.4 ...
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... STOPB DEVSELB CLK 1 FRAMEB IRDYB TRDYB DEVSELB Integrated Gigabit Ethernet Controller (LOM Figure 25. Target Initiated Termination - Abort FAST MED SLOW Figure 26. Master Initiated Termination - Abort 36 RTL8110SB(L) Datasheet RESPONSE SUB ACKNOWLEDGE Track ID: JATR-1076- Rev. 1.4 ...
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... CLK 2 1 FRAMEB AD ADDRESS C/BE# BUS CMD PAR/PAR64 SERR# PERR# Integrated Gigabit Ethernet Controller (LOM DATA ADDRESS BE# BUS CMD Figure 27. Parity Operation – One Example 37 RTL8110SB( DATA BE# Track ID: JATR-1076-21 Datasheet 10 Rev. 1.4 ...
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... HI-ADDR DATA-1 BUS CMD Figure 28. Memory Read Above 4GB (DAC HI-ADDR DATA-1 DATA-2 BUS CMD BE3-0B-1 BE3-0B-2 Figure 29. Memory Write Above 4GB (DAC) 38 RTL8110SB( DATA-2 DATA-3 BE3- DATA-3 BE3-0B-3 Track ID: JATR-1076-21 Datasheet 10 10 ...
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... Mechanical Dimensions 8.1. 128-Pin QFP Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Integrated Gigabit Ethernet Controller (LOM) 39 Track ID: JATR-1076-21 RTL8110SB(L) Datasheet Rev. 1.4 ...
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... Dimension b does not include dambar protrusion/intrusion. 0.10 0.25 0.91 3. Controlling dimension: Millimeter 2.60 2.85 3.10 4. General appearance spec. Should be based on final 0.12 0.32 0.22 0.05 0.15 0.25 13.75 14.00 14.25 TITLE: 128 QFP (14x20 mm) PACKAGE OUTLINE 19.75 20.00 20.25 0.25 0.5 0.75 16.90 17.20 17.50 APPROVE 22.90 23.20 23.50 0.68 0.88 1.08 1.35 1.60 1.85 CHECK - - 0.10 0° - 12° REALTEK SEMICONDUCTOR CORP. 40 RTL8110SB(L) : visual inspection. -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL DOC. NO. VERSION PAGE DWG NO. DATE Track ID: JATR-1076-21 Datasheet Q128 - 1 Rev. 1.4 ...
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... LQFP Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Integrated Gigabit Ethernet Controller (LOM) 41 Track ID: JATR-1076-21 RTL8110SB(L) Datasheet Rev. 1.4 ...
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... Millimeter 0.00 - 0.25 3. General appearance spec. Should be based on final 1.30 1.40 1.50 0.15 0.29 0.22 0.09 - 0.20 TITLE : 128LD LQFP ( 14x20x1.4 mm*2 ) PACKAGE 14.00 14.25 20.00 20.25 0.50 BSC APPROVE 16.00 16.30 22.00 23.30 0.45 0.75 CHECK 0.60 1.00 REF REALTEK SEMICONDUCTOR CORP. 0° 3.5° 9° 42 RTL8110SB(L) visual inspection. OUTLINE -CU L/F, FOOTPRINT 2.0 mm LEADFRAME MATERIAL DOC. NO. VERSION PAGE DWG NO. DATE Track ID: JATR-1076-21 Datasheet LQ128 - 1 Rev. 1.4 ...
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... Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw Integrated Gigabit Ethernet Controller (LOM) Table 20. Ordering Information Package 128-pin QFP 128-pin LQFP 128-pin QFP 128-pin LQFP 43 RTL8110SB(L) Datasheet Status Track ID: JATR-1076-21 Rev. 1.4 ...