AX88195P ASIX, AX88195P Datasheet
AX88195P
Available stocks
Related parts for AX88195P
AX88195P Summary of contents
Page 1
... Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respective holders. BUFFER SRAM Addr L AX88195 FAX: 886-3-579-9558 AX88195P PHY/TxRx RJ45 First Released Date : Oct/02/1998 http://www.asix.com.tw ...
Page 2
... RITE 0CH (R ) .................................................................................. 19 FFSET EAD 16H ( ...................................................................................... 20 EAD RITE 1(IFGS1) O 12H (R /W FFSET EAD 2(IFGS2) O 13H (R /W FFSET EAD R (MEMR) O 14H (R EGISTER FFSET 15H (W ) ................................................................................................... 20 RITE . ................................................................................................................... 21 ......................................................................................................... 21 ...................................................................................................... 22 . .................................................................................................... 22 ........................................................................................................................ 23 ................................................................................................................... 23 ....................................................................................................................... 24 2 ................................................................ 13 ) ..................................................................... 17 )....................................................................... 18 )................................................................ 18 RITE ) ............................................................... 20 RITE ) ............................................................... 20 RITE /W ) .............................................. 20 EAD RITE ASIX ELECTRONICS CORPORATION ...
Page 3
... APPLICATION WITH U C ................................................................................................... 35 SING RYSTAL FIGURES ............................................................................................................................. 4 D .............................................................................................................. 5 IAGRAM D ISA B M ............................................................................... 6 IAGRAM FOR US ODE .................................................................................. 7 IAGRAM FOR X ODE D MC68K M ................................................................................ 8 IAGRAM FOR ODE D MCS-51 M ............................................................................... 9 IAGRAM FOR ODE TABLES .................................................................................................. 11 ..................................................................................................................... 11 ..................................................................................................... 12 ...................................................................................................................... 12 ......................................................................................................................... ..................................................................................................... 13 ETUP ABLE ............................................................................................................................ 14 M .................................................................................................. 15 APPING M ................................................................................................ 16 APPING 3 ASIX ELECTRONICS CORPORATION ...
Page 4
... AX88195 use 128-pin LQFP low profile package, 25MHz operation, dual 5V and 3.3V CMOS process with 5V I/O tolerance or pure 3.3V operation. 1.2 AX88195 Block Diagram: EECS EECK EEDI EEDO NE2000 Registers Fig - 1 AX88195 Block Diagram MEMA[15:1] SRAM Arbiter SEEPROM I/F Remote DMA FIFOs Host Interface Ctl BUS 4 MEMD[15:0] STA MAC Core SA[9:0] SD[15:0] ASIX ELECTRONICS CORPORATION MII I/F ...
Page 5
... Fig - 2 AX88195 Pin Connection Diagram AX88195 CONTROLLER 5 HVDD 64 MEMD[14] 63 MEMD[15] 62 MEMA[1] 61 MEMA[2] 60 VSS 59 MEMA[3] 58 MEMA[4] 57 MEMA[ MEMA[6] LVDD 54 MEMA[7] 53 MEMA[8] 52 MEMA[9] 51 MEMA[10] 50 VSS 49 MEMA[11] 48 MEMA[12] 47 MEMA[13] 46 MEMA[14] 45 LVDD 44 MEMA[15] 43 /MEMRD 42 /MEMWR 41 VSS SD[0] 38 SD[1] 37 SD[2] 36 SD[3] 35 VSS 34 SD[4] 33 ASIX ELECTRONICS CORPORATION ...
Page 6
... Fig - 3 AX88195 Pin Connection Diagram for ISA Bus Mode AX88195 CONTROLLER 6 HVDD 64 MEMD[14] 63 MEMD[15] 62 MEMA[1] 61 MEMA[2] 60 VSS 59 MEMA[3] 58 MEMA[4] 57 MEMA[5] 56 MEMA[6] 55 LVDD 54 MEMA[7] 53 MEMA[8] 52 MEMA[9] 51 MEMA[10] 50 VSS 49 MEMA[11] 48 MEMA[12 MEMA[13] MEMA[14] 45 LVDD 44 MEMA[15] 43 /MEMRD 42 /MEMWR 41 VSS SD[0] 38 SD[1] 37 SD[2] 36 SD[3] 35 VSS 34 SD[4] 33 ASIX ELECTRONICS CORPORATION ...
Page 7
... Fig - 4 AX88195 Pin Connection Diagram for 80x86 Mode AX88195 CONTROLLER 7 HVDD 64 MEMD[14] 63 MEMD[15] 62 MEMA[1] 61 MEMA[2] 60 VSS 59 MEMA[3] 58 MEMA[4] 57 MEMA[5] 56 MEMA[6] 55 LVDD 54 MEMA[7] 53 MEMA[8] 52 MEMA[9] 51 MEMA[10] 50 VSS 49 MEMA[11] 48 MEMA[12] 47 MEMA[13] 46 MEMA[14] 45 LVDD 44 MEMA[15] 43 /MEMRD 42 /MEMWR 41 VSS SD[0] 38 SD[1] 37 SD[2] 36 SD[3] 35 VSS 34 SD[4] 33 ASIX ELECTRONICS CORPORATION ...
Page 8
... Fig - 5 AX88195 Pin Connection Diagram for MC68K Mode AX88195 LOCAL CPU BUS CONTROLLER 8 HVDD 64 MEMD[14] 63 MEMD[15] 62 MEMA[1] 61 MEMA[2] 60 VSS 59 MEMA[3] 58 MEMA[4] 57 MEMA[5] 56 MEMA[6] 55 LVDD 54 MEMA[7] 53 MEMA[8] 52 MEMA[9] 51 MEMA[10] 50 VSS 49 MEMA[11] 48 MEMA[12] 47 MEMA[13] 46 MEMA[14 LVDD MEMA[15] 43 /MEMRD 42 /MEMWR 41 VSS SD[0] 38 SD[1] 37 SD[2] 36 SD[3] 35 VSS 34 SD[4] 33 ASIX ELECTRONICS CORPORATION ...
Page 9
... VSS 119 NC 120 SAX[2] 121 SAX[3] 122 /CS 123 /PSEN 124 NC 125 /RESET 126 RESET 127 LVDD 128 Fig - 6 AX88195 Pin Connection Diagram for MCS-51 Mode AX88195 9 ASIX ELECTRONICS CORPORATION 64 HVDD MEMD[14] 63 MEMD[15] 62 MEMA[1] 61 MEMA[2] 60 VSS 59 MEMA[3] 58 MEMA[4] 57 MEMA[ MEMA[6] LVDD 54 ...
Page 10
... When Motorola CPU type is select , the pin is useless. 14 I/O Write :The host asserts /IOWR to write data into AX88195 I/O space. When Motorola CPU type is select, the pin is active high for read operation at the same time. 10 Pull Up Pull Down P Power Pin DESCRIPTION ASIX ELECTRONICS CORPORATION ...
Page 11
... All data transfers on MDIO are synchronized to the rising edge of this clock. MDC is a 2.5MHz frequency clock output. 91 Station Management Data Input / Output : Serial data input/output transfers from/to the PHYs . The transfer protocol conforms to the IEEE 802.3u MII specification. 11 DESCRIPTION ASIX ELECTRONICS CORPORATION ...
Page 12
... Reset is active low then place AX88195 into reset mode immediately. During rising edge the AX88195 loads the power on setting data. User can select either RESET or /RESET for applications. No Connection : for manufacturing test only. 39 44, 54, Power Supply : +3.3V DC. 128 12 DESCRIPTION DESCRIPTION DESCRIPTION ASIX ELECTRONICS CORPORATION ...
Page 13
... SAX[2] address decode depends on MEMD[11] power on value SAX[1] address decode depends on MEMD[10] power on value SAX[0] address decode depends on MEMD[9] power on value MEMD[8] MEMD[ IO_BASE 0 300h 1 320h 0 340h 1 360h 0 380h 1 3A0h 0 200h 1 220h CPU TYPE ISA BUS 80186 MC68K MCS-51 (805X) ASIX ELECTRONICS CORPORATION ...
Page 14
... User can define by themselves and can access via I/O address offset 14H MII/EEPROM registers 3.2 I/O Mapping SYSTEM I/O OFFSET 0000H 001FH Tab - 7 I/O Address Mapping 3.3 SRAM Memory Mapping OFFSET 4000H 7FFF 0000H FFFFH Tab - 8 Local Memory Mapping FUNCTION MAC CORE REGISTER FUNCTION NE2000 COMPATABLE MODE SRAM BUFFER EXTENSION MODE 32K X 16 SRAM BUFFER 14 ASIX ELECTRONICS CORPORATION ...
Page 15
... Remote Byte Count 0 ( RBCR0 ) Remote Byte Count 1 ( RBCR1 0 Receive Configuration Register ( RCR ) Transmit Configuration Register ( TCR ) Data Configuration Register ( DCR ) Interrupt Mask Register ( IMR ) Data Port IFGS1 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) Reserved Reserved 15 WRITE ASIX ELECTRONICS CORPORATION ...
Page 16
... Multicast Address Register 3 ( MAR3 ) Multicast Address Register 4 ( MAR4 ) Multicast Address Register 5 ( MAR5 ) Multicast Address Register 6 ( MAR6 ) Multicast Address Register 7 ( MAR7 ) Data Port Inter-frame Gap Segment 1 IFGS1 Inter-frame Gap Segment 2 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) Reserved Reserved 16 WRITE ASIX ELECTRONICS CORPORATION ...
Page 17
... Indicates packet transmitted with no error 0 PRX Packet Received Indicates packet received with no error. DESCRIPTION PS0 0 page 0 1 page Not allowed 0 1 Remote Read 1 0 Remote Write 1 1 Not allowed X X Abort / Complete Remote DMA DESCRIPTION FIFO Underrun 17 ASIX ELECTRONICS CORPORATION ...
Page 18
... These encoded configuration bits set the type of loop-back that performed. Mode 0 Mode 1 Mode 2 0 CRC Inhibit CRC 0 : CRC appended by transmitter CRC inhibited by transmitter. DESCRIPTION DESCRIPTION DESCRIPTION LB1 LB0 0 0 Normal operation 0 1 Internel NIC loop-back 1 0 PHYcevisor loop-back 18 ASIX ELECTRONICS CORPORATION ...
Page 19
... Enable the receiver to accept and save packets with error. 4.8 Receive Status Register (RSR) Offset 0CH (Read) FIELD NAME 7 - Reserved 6 DIS Receiver Disabled 5 PHY Multicast Address Received. 4 MPA Missed Packet 3 FO FIFO Overrun 2 FAE Frame alignment error CRC error. 0 PRX Packet Received Intact DESCRIPTION DESCRIPTION DESCRIPTION 19 ASIX ELECTRONICS CORPORATION ...
Page 20
... MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit let MDIO as output signal. 0 MDC MDC MII Clock 4.13 Test Register (TR) Offset 15H (Write) FIELD NAME 7:5 - Reserved 4 TF16T Test for Collision 3 TPE Test pin Enable 2:0 IFG Select Test Pins Output DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 20 ASIX ELECTRONICS CORPORATION ...
Page 21
... SD[15:8] SD[7:0] High-Z High-Z Not Valid Even-Byte Not Valid Odd-Byte Odd-Byte Even-Byte SD[15:8] SD[7: Even-Byte X Odd-Byte Odd-Byte Even-Byte SD[15:8] SD[7:0] High-Z High-Z Not Valid Even-Byte Odd-Byte Not Valid Odd-Byte Even-Byte SD[15:8] SD[7: Even-Byte Odd-Byte X Odd-Byte Even-Byte ASIX ELECTRONICS CORPORATION ...
Page 22
... SA0 /IORD /IOWR SD[15:8] SD[7:0] High-Z High-Z Not Valid Odd-Byte Even-Byte Not Valid Even-Byte Odd-Byte SD[15:8] SD[7: Odd-Byte Even-Byte X Even-Byte Odd-Byte SD[15:8] SD[7:0] High-Z High-Z High-Z High-Z Not Valid Even-Byte Not Valid Odd-Byte SD[15:8] SD[7: Even-Byte X Odd-Byte ASIX ELECTRONICS CORPORATION ...
Page 23
... Voh Vdd-0.4 Iil -1 Iol -1 SYM Min Tpy Vil - Vih 1.9 Vol - Voh Vdd-0.4 Iil -1 Iol -1 SYM Min Tpy DPt5v 20 DPt3v 38 SPt3v 46 23 ASIX ELECTRONICS CORPORATION Max Units +85 C +150 +4.6 V HVdd+0.5 V LVdd+0.5 V HVdd+0.5 V LVdd+0.5 V +220 C Max Units +75 C +5.25V V +3.30 V +3.60 V Max Units 0 ...
Page 24
... Tod LCLK/XTALIN TO CLK25M OUT DELAY (INVERTED) 6.4.2 Reset Timing LCLK/XTALIN RESET /RESET Symbol Description Trst Reset pulse width Thigh Tf Tlow Tcyc Min Min 100 24 Typ. Max Units Typ. Max Units - - LClk ASIX ELECTRONICS CORPORATION ...
Page 25
... Note : for byte access minimum is 90ns, for word access minimum is 50 ns. Th(AEN) Tsu(A) Th(A) Tv(CS16-A) Ten(RD) Tw(RW) Tdis(RDY) Tdis(RD) DATA Valid Tsu(WR) DATA Input Establish Min 0 *90 25 Tdis(CS16-A) Th(WR) Typ. Max Units - - ASIX ELECTRONICS CORPORATION ...
Page 26
... OR /IOWR WIDTH TIME * Note : for byte access minimum is 90ns, for word access minimum is 50 ns. Tsu(A) Th(A) Tdis(RDY) Ten(RD) Tdis(RD) DATA Valid Tsu(WR) DATA Input Establish Min 0 *90 26 Th(WR) Typ. Max Units - - ASIX ELECTRONICS CORPORATION ...
Page 27
... Tw(DS) /UDS OR /LDS WIDTH TIME * Note : for byte access minimum is 90ns, for word access minimum is 50 ns. Tsu(A) Th(A) Tw(DS) Ten(DS) Tdis(DTACK) Tdis(DS) DATA Valid Tsu(DS) DATA Input Establish Min 0 *90 27 ASIX ELECTRONICS CORPORATION Tdis(WR-DS) Th(DS) Typ. Max Units - - ...
Page 28
... OUTPUT DISABLE TIME FROM /IORD Tsu(WR) DATA SETUP TIME Th(WR) DATA HOLD TIME Tw(RW) /IORD OR /IOWR WIDTH TIME Th(PSEN) Tsu(A) Th(A) Ten(RD) Tw(RW) Tdis(RDY) Tdis(RD) DATA Valid Tsu(WR) DATA Input Establish Min 0 Th(WR) Typ. Max Units - - ASIX ELECTRONICS CORPORATION ...
Page 29
... Ttclk Ttch Ttcl Ttv Trclk Trch Trcl Trs Trs1 Min - - 14 140 14 140 - 140 14 140 Tth Trh Typ. Max Units 400 - 260 260 400 - 260 260 ASIX ELECTRONICS CORPORATION ...
Page 30
... NOTE : All most any brand asynchronous SRAM access time under 20 ns can fit into the specification. Tsu(A) Th(A) Tw(WR) Td(WtoR) Tw(RDdis) Tsu(D) Th(D) DATA Valid Min Typ 0 0.3 - Th(A) Tw(RD) ( High Level ) ( Low Level ) Tsu(RD) Th(RD) Valid DATA Min Typ 1 ASIX ELECTRONICS CORPORATION Max Units - 4 Max Units - ...
Page 31
... AX88195 Local CPU Bus Fast Ethernet MAC Controller 7.0 Package Information pin 1 b SYMBOL MILIMETER MIN. NOM 0.1 1.3 1.4 0.155 0.16 13.90 14.00 13.90 14.00 0.40 15.60 16.00 15.60 16.00 0.30 0.50 1. ASIX ELECTRONICS CORPORATION MAX 1.5 1.7 0.26 14.10 14.10 16.40 16.40 0.70 10 ...
Page 32
... Crystal 8pf 2Mohm Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided by crystal supplier. A.2 Using Oscillator AX88195 XTALIN 3.3V Power OSC 25MHz To PHY CLKO25M XTALOUT 8pf To PHY CLKO25M XTALOUT NC 32 ASIX ELECTRONICS CORPORATION ...
Page 33
... AX88195 Local CPU Bus Fast Ethernet MAC Controller A.3 Dual power (5V and 3.3V/3.0V) application +5V +5V HVdd +3.3V LVdd A.4 Single power (3.3V/3.0V) application +3.3V +3.3V HVdd +3.3V LVdd RJ45 MAGNETIC PHY/TxRx Optional EEPROM AX88195 +5V CPU I/F RJ45 MAGNETIC PHY/TxRx Optional EEPROM AX88195 +3.3V CPU I/F 33 ASIX ELECTRONICS CORPORATION +5V +5V +5V SRAM +3.3V +3.3V +3.3V SRAM ...
Page 34
... A.5 Dual power (5V and 3.3V) application with 3.3V PHY The 510 and 1K Ohm resisters are just for voltage adjustment RXD[3:0] RX_DV RX_ER RX_CLK TX_EN TXD[3:0] TX_CLK MDIO AX88195 CRS COL MDC 510 ohm 34 RXD[3:0] CRS RX_DV RX_ER RX_CLK COL TX_EN TXD[3:0] TX_CLK MDC MDIO 1k ohm PHY ASIX ELECTRONICS CORPORATION ...
Page 35
... Solution: Change the value of capacitors beside crystal as below: XIN Note: The capacitors may be various depend on the specification of crystal. While designing, please refer to the circuit provided by crystal supplier. Y1 XOUT 25MHZ R4 2M C22 C23 18p 18p 35 ASIX ELECTRONICS CORPORATION Date: May 21, 1999 ...
Page 36
... Set Remote DMA Byte Count low byte = 40h ; Index = 30Bh ; ; Set Remote DMA Byte Count high byte = 00h ; Index = 300h ; ; Set remote DMA read command ; Insert wait state here ; Insert more wait states again if necessary ; Index = 310h ; Set Rx Buffer Address ; Set Rx Length ; Read data port 36 ASIX ELECTRONICS CORPORATION ...
Page 37
... DTACK can’t fit 68K CPU timing in 68K mode Solution : Using the DTACK automatic insertion function in 68K CPU. Mov dx,307h Mov al,3 ; clear Tx/Rx interrupt Out dx,al ; output to clear ISR In al,dx ; read ISR Test al,3 ; Check ISR cleared or not Jz ClrISRDone ; Clear ok Mov al not, clear again Out dx,al Jmp ClrISR … ; clear successful 37 ASIX ELECTRONICS CORPORATION ...