SST49LF040A-33-4C-NH Silicon Storage Technology, Inc., SST49LF040A-33-4C-NH Datasheet
SST49LF040A-33-4C-NH
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SST49LF040A-33-4C-NH Summary of contents
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A SST49LF030A / SST49LF040A / SST49LF080A3 Mbit LPC Flash FEATURES: • LPC Interface Flash – SST49LF030A: 384K x8 (3 Mbit) SST49LF040A: 512K x8 (4 Mbit) SST49LF080A: 1024K x8 (8 Mbit) • Conforms to Intel LPC Interface Specification 1.0 • Flexible Erase Capability – ...
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... System Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Response To Invalid Fields Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Registers General Purpose Inputs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A 2 S71206-01-000 1/02 554 ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Byte-Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sector-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chip-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data# Polling ( Toggle Bit ( Data Protection (PP Mode Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Software Data Protection (SDP SOFTWARE COMMAND SEQUENCE ...
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... FIGURE 1: Pin Assignments for 32-lead TSOP (8mm x 14mm FIGURE 2: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 3: Device Memory Map for SST49LF030A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FIGURE 4: Device Memory Map for SST49LF040A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FIGURE 5: Device Memory Map for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FIGURE 6: LPC Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FIGURE 7: LPC Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIGURE 8: Program Command Sequence (LPC Mode) ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A LIST OF TABLES TABLE 1: Pin Description TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3: SST49LF030A / SST49LF040A Address bits definition TABLE 4: SST49LF080A Address bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 5: Address Decoding Range for SST49LF030A / SST49LF040A . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 6: Address Decoding Range for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 7: LPC Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 8: LPC Write Cycle ...
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... LFRAME# Interface ID[3:0] GPI[4:0] R/C# A[10:0] Programmer DQ[7:0] Interface OE# WE# ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A X-Decoder Address Buffers & Latches Control Logic MODE RST# CE# 6 SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 554 ILL B1.1 S71206-01-000 1/02 554 ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A PIN ASSIGNMENTS (CE#) 4 MODE (MODE) 5 A10 (GPI4) 6 R/C# (LCLK RST# (RST (GPI3 (GPI2 (GPI1 (GPI0 (WP (TBL Designates LPC Mode FIGURE ...
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... NC No Connection I 1. I=Input, O=Output ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Interface PP LPC Functions X Inputs for low-order addresses during Read and Write operations. Addresses are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A DEVICE MEMORY MAPS TBL# WP# for Block 2~6 * operations to shaded area are not valid. FIGURE EVICE EMORY TBL# WP# FIGURE EVICE EMORY ©2002 Silicon Storage Technology, Inc. 7FFFFH Block 7 70000H 6FFFFH Block 6 ...
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... Advance Information TBL# WP# for Block 0~14 FIGURE EVICE EMORY ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A 0FFFFFH Block 15 0F0000H 0EFFFFH Block 14 0E0000H 0DFFFFH Block 13 0D0000H 0CFFFFH Block 12 0C0000H 0BFFFFH Block 11 0B0000H 0AFFFFH Block 10 0A0000H ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A DESIGN CONSIDERATIONS SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between V V less than 1 cm away from the V SS Additionally, a low frequency 4.7 µF electrolytic capacitor from should be placed within the V ...
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... The SST49LF030A features are equivalent to the SST49LF040A with 128 KByte less memory. For the SST49LF030A, operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map). 2. See Table 9 for multiple device selection configuration. TABLE 4: SST49LF080A A ...
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... Memory Access Register Access Device # Memory Access Register Access 1. The SST49LF030A features are equivalent to the SST49LF040A with 128 KByte less memory. For the SST49LF030A, operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map). TABLE ...
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... LAD[3:0] 1 Direction Comments IN LFRAME# must be active (low) for the SST49LF040A to respond. Only the last start field (before LFRAME# transitioning high) should be recognized. IN Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved. ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A TABLE 8: LPC W C RITE YCLE Clock Field Field Contents Cycle Name LAD[3:0] 1 START 2 CYCTYPE + DIR 3-10 ADDRESS 11 DATA 12 DATA 13 TAR0 14 TAR1 1111 (float) 15 SYNC 16 TAR0 17 TAR1 1111 (float) 1. Field contents are valid on the rising edge of the present clock cycle. ...
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... Address out of range: The SST49LF0x0A will only response to address range as specified in Tables 5 and 6. The SST49LF030A features are equivalent to the SST49LF040A with 128 KByte less memory. For the SST49LF030A, operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map). ...
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... The SST49LF030A features are equivalent to the SST49LF040A with 128 KByte less memory. For the SST49LF030A, operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map). Registers There are two registers available on the SST49LF0x0A, the General Purpose Inputs Registers (GPI_REG) and the JEDEC ID Registers ...
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... The SST49LF030A features are equivalent to the SST49LF040A with 128 KByte less memory. For the SST49LF030A, operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map. ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A TABLE 12 EMORY AP EGISTER Device # 0 (Boot device PARALLEL PROGRAMMING MODE Device Operation Commands are used to initiate the memory operation func- tions of the device. The data portion of the software com- mand sequence is latched on the rising edge of WE# ...
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... Any commands written during the Chip-Erase operation will be ignored. ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Write Operation Status Detection The SST49LF0x0A devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time ...
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... X can but no other value Device ID 1CH for SST49LF030A, 53H for SST49LF040A and 5BH for SST49LF080A Data Protection (PP Mode) The SST49LF0x0A devices provide both hardware and software features to protect nonvolatile data from inadvert- ent writes. Hardware Data Protection Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle ...
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... Device ID = 53H, are read with With 49LF080A Device ID = 5BH, are read with Both Software ID Exit operations are equivalent ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A S EQUENCE 1 1 2nd 3rd Cycle Cycle 2 2 ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 2nd Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# 3rd Start LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock ...
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... Clock 1 Clock Note1: Address must be within memory address range specified in Tables 4 and 5. FIGURE ATA OLLING OMMAND ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Address 1 A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] Load Address in 8 Clocks Load Data in 2 Clocks Write the last command (Program or Erase) to the device in LPC mode. ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock Note 1: Address must be within memory address range specified in Tables 4 and 5 ...
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... Note 1: Address must be within memory address range specified in Tables 4 and 5. FIGURE 11 ECTOR RASE OMMAND ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Address 1 A[23:20] A[19:16] 0101b 0101b 0101b 0101b Load Address "YYYY 5555H" Clocks Load Data "AAH" Clocks Write the 1st command to the device in LPC mode ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 2nd Start Cycle 0000b 011Xb A[31:28] A[27:24] LAD[3:0] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 3rd Start Cycle LAD[3:0] 0000b ...
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... Read Start Cycle LAD[3:0] 0000b 010Xb 1 Clock 1 Clock Note1: See Tables 10 and 11 for Register Addresses FIGURE 13 EGISTER EADOUT ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Address 1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks C S (LPC M OMMAND EQUENCE ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A ELECTRICAL SPECIFICATIONS The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) as defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 15 for the DC voltage and current speci- fications. Refer to Tables 19 through 22 and Tables 24 through 26 for the AC timing specifications for Clock, Read, Write, and Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “ ...
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... I/O Pin Capacitance I Input Capacitance IN 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A ( NTERFACES Limits Min Max ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A TABLE 18 ELIABILITY HARACTERISTICS Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 19: C ...
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... There may be additional latency due toT V DD CLK RST#/INIT# LAD[3:0] LFRAME# FIGURE 15 ESET IMING IAGRAM ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A , V =3.0-3.6V (LPC M ) ODE reset procedure is performed during a Program or Erase operation. RSTE T PRST T KRST T RSTP T ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A AC Characteristics TABLE 21 EAD RITE YCLE Symbol Parameter T Clock Cycle Time CYC T Data Set Up Time to Clock Rising SU T Clock Rising to Data Hold Time Clock Rising to Data Valid VAL T Byte Programming Time ...
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... Production testing may use MAX different voltage values, but must correlate results back to these parameters ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A V LCLK TEST T ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A TABLE 24 EAD YCLE IMING Symbol Parameter T Read Cycle Time RC T RST# High to Row Address Setup RST T R/C# Address Set-up Time AS T R/C# Address Hold Time AH T Address Access Time AA T Output Enable Access Time ...
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... Addresses R/ WE# OE# High-Z DQ 7-0 FIGURE 19 EAD YCLE IMING ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A , V =3.0-3.6V ( ODE reset procedure is performed during a Program or Erase operation. RSTE RSTC T PRST T RSTP T RSTF ( ODE ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A T RST RST# Addresses R/C# OE# WE# DQ 7-0 FIGURE 20 RITE YCLE IMING Row Addresses R/C# WE# OE FIGURE 21 ATA OLLING IMING ©2002 Silicon Storage Technology, Inc. Row Address Column Address ...
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... MS-0 R/C# OE# WE Byte-Program Address A = Most Significant Address MS FIGURE 23 YTE ROGRAM IMING ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A T OET D ( IAGRAM ODE 2AAA 5555 ( IAGRAM ODE 38 D 554 ILL F22.0 ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A A 14-0 (Internal A ) 5555 MS-0 R/C# OE Sector Address X FIGURE 24 ECTOR RASE IMING A 14-0 (Internal A ) 5555 MS-0 R/C# OE Block Address X FIGURE 25 LOCK RASE IMING ©2002 Silicon Storage Technology, Inc. 2AAA 5555 5555 55 80 ...
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... HIP RASE IMING A 14-0 (Internal A ) 5555 MS-0 R/ 7-0 Device ID: 1CH for SST49LF030A, 53H for SST49LF040A FIGURE 27 OFTWARE NTRY AND ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A 2AAA 5555 5555 ( IAGRAM ODE ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A A 14-0 (Internal A ) MS-0 R/C# OE# WE# DQ 7-0 FIGURE 28 OFTWARE XIT V IHT INPUT V ILT AC test inputs are driven at V (0.9 V IHT points for inputs and outputs are V FIGURE 29 NPUT UTPUT TO DUT FIGURE 30 EST ...
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... ILL F31.0 FIGURE 31 EAD LOWCHART (LPC M ) ODE ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: A0H Cycle: 3 Address: A ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Command Sequence Address: 2AAAH Address: 2AAAH FIGURE 33 RASE OMMAND ©2002 Silicon Storage Technology, Inc. Block-Erase Sector-Erase Command Sequence Address: 5555H Address: 5555H Write Data: AAH Write Data: AAH Cycle: 1 Cycle: 1 Address: 2AAAH ...
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... Cycle: 5 Available for Next Command FIGURE 34 OFTWARE RODUCT ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Software Product ID Exit Command Sequence Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A FIGURE 35 YTE ROGRAM OMMAND ©2002 Silicon Storage Technology, Inc. Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of ...
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... T SCE Program/Erase Completed FIGURE 36 AIT PTIONS LOWCHART ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Toggle Bit Byte- Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Program/Erase Completed ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Software Product ID Entry Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 90H Address: 5555H Wait T IDA Read Software ID FIGURE 37 OFTWARE RODUCT ©2002 Silicon Storage Technology, Inc. ...
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... Chip erased to FFH FIGURE 38 RASE OMMAND ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Block-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH ...
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... XX Valid combinations for SST49LF030A SST49LF030A-33-4C-WH SST49LF030A-33-4C-NH Valid combinations for SST49LF040A SST49LF040A-33-4C-WH SST49LF040A-33-4C-NH Valid combinations for SST49LF080A SST49LF080A-33-4C-WH SST49LF080A-33-4C-NH Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ...
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... LEAD LASTIC EAD HIP ARRIER SST ACKAGE ODE ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A SIDE VIEW .112 .106 .029 .040 .020 R. x 30˚ MAX. .023 .030 .021 .013 .400 .032 BSC ...
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... Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A Pin # 1 Identifier 12.50 12.30 0.70 0.50 14.20 13.80 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. ...
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... Advance Information Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2002 Silicon Storage Technology, Inc. 3 Mbit / 4 Mbit / 8 Mbit LPC Flash SST49LF030A / SST49LF040A / SST49LF080A www.SuperFlash.com or www.sst.com 52 S71206-01-000 1/02 554 ...