K7N161801A-QC25 Samsung, K7N161801A-QC25 Datasheet

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K7N161801A-QC25

Manufacturer Part Number
K7N161801A-QC25
Description
IC SRAM CHIP SYNC SINGLE 2.5V 16MBIT 1MX16 2.6NS 100TQFP
Manufacturer
Samsung
Datasheet
K7N167245A
Document Title
Revision History
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
256Kx72-Bit Pipelined NtRAM
Rev. No.
0.0
0.1
0.2
0.3
History
1. Initial document.
1. Add JTAG Scan Order
1. Upate DC characteristics(icc,isb)
1. Speed bin merge.
2. AC parameter change.
From K7N167249A to K7N167245A.
tOH(min)/tLZC(min) from 0.8 to 1.5 at -25
tOH(min)/tLZC(min) from 1.0 to 1.5 at -22
tOH(min)/tLZC(min) from 1.0 to 1.5 at -20
TM
- 1 -
256Kx72 Pipelined NtRAM
April. 21. 2001
May. 10. 2001
Aug. 30. 2001
Dec. 26. 2001
Draft Date
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Remark
Dec. 2001
Rev 0.3
TM

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K7N161801A-QC25 Summary of contents

Page 1

... The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques- tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. ...

Page 2

... K7N167245A 16Mb NtRAM(Flow Through / Pipelined) , Double Late Write RAM x72 Ordering Informa Org. Part Number K7M161825A-Q(H/F)C(I)65/75/85 1Mx18 K7N161801A-Q(H/F)C(I)25/22/20/16/13 K7N161845A-Q(H/F)C(I)25/22/20/16/13 K7M163225A-QC(I)65/75/85 512Kx32 K7N163201A-QC(I)25/22/20/16/13 K7N163245A-QC(I)25/22/20/16/13 K7M163625A-Q(H/F)C(I)65/75/85 512Kx36 K7N163601A-Q(H/F)C(I)25/22/20/16/13 K7N163645A-Q(H/F)C(I)25/22/20/16/13 K7N167245A-HC25/22/20/16/13 256Kx72 K7Z167285A-HC30/27/25 256Kx72 Pipelined NtRAM Speed Mode VDD FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3 ...

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... LBO BURST ADDRESS COUNTER WRITE WRITE ADDRESS ADDRESS REGISTER REGISTER CONTROL LOGIC NtRAM and No Turnaround Random Access Memory are trademarks of Samsung Preliminary TM 256K x 72 MEMORY ARRAY DATA-IN K REGISTER DATA-IN K REGISTER OUTPUT K REGISTER BUFFER 72 Dec. 2001 Rev 0.3 ...

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K7N167245A 209BGA PACKAGE PIN CONFIGURATIONS K7N167245A(256K x 72 DQg DQg A B DQg DQg BWc C DQg DQg BWh D DQg DQg DQPg DQPc V DDQ F DQc DQc DQc ...

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K7N167245A FUNCTION DESCRIPTION The K7N167245A is NtRAM TM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are ...

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K7N167245A BEGIN READ READ BURST BURST READ COMMAND DS READ WRITE BURST Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not ...

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K7N167245A TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADV WE BWx ...

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K7N167245A ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on Any Other Pin Relative Power ...

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K7N167245A DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ Output Leakage Current I OL Operating Current Standby Current I SB1 I SB2 Output Low Voltage V OL Output High Voltage V OH Input ...

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K7N167245A Output Load(A) Dout Zo=50 AC TIMING CHARACTERISTICS (V =2.5V 5 PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output ...

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K7N167245A SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SLEEP MODE is dictated by the length of time the High state. After ...

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K7N167245A IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing ...

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... C 67 103 104 105 Preliminary TM Boundary Scan 122 bits Samsung JEDEC Code Start Bit(0) (11: 1) 00001001110 1 CS DQPh 2R 106 DQPd 1R 107 DQd 1T 108 A DQd 2T 109 DQg DQd 2U 110 DQg ...

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K7N167245A JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage Output Low Voltage NOTE : The input level of SRAM pin is to follow the SRAM DC specification 1. In Case of ...

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K7N167245A 256Kx72 Pipelined NtRAM - 15 - Preliminary TM Dec. 2001 Rev 0.3 ...

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K7N167245A 256Kx72 Pipelined NtRAM - 16 - Preliminary TM Dec. 2001 Rev 0.3 ...

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K7N167245A 256Kx72 Pipelined NtRAM - 17 - Preliminary TM Dec. 2001 Rev 0.3 ...

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K7N167245A 256Kx72 Pipelined NtRAM - 18 - Preliminary TM Dec. 2001 Rev 0.3 ...

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K7N167245A 256Kx72 Pipelined NtRAM - 19 - Preliminary TM Dec. 2001 Rev 0.3 ...

Page 20

K7N167245A 209 Bump BGA PACKAGE DIMENSIONS 14mm x 22mm Body, 1.0mm Bump Pitch, 11x19 Bump Array 14.00 Indicator of Ball(1A) Location C1.00 12.50 256Kx72 Pipelined NtRAM 1.00x10=10.00(BSC) 1.00(BSC) C0.70 NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball ...

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