AT89C51AC2 Atmel Corporation, AT89C51AC2 Datasheet
AT89C51AC2
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AT89C51AC2 Summary of contents
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... While remaining fully compatible with the 80C52, the T8C51AC2 offers a superset of this standard microcontroller mode, a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Enhanced 8-bit Microcontroller with 32 KB Flash Memory AT89C51AC2 T89C51AC2 Rev. 4127H–8051–02/08 1 ...
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Block Diagram XTAL1 XTAL2 ALE PSEN CPU Notes analog Inputs/8 Digital I/O 2. 2-Bit I/O Port A/T89C51AC2 2 RAM Flash Boot EE UART 256x8 32kx loader PROM 8 2kx8 2kx8 C51 CORE IB-bus Timer 0 ...
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Pin Configuration 4127H–8051–02/08 P1.4/AN4/CEX1 7 P1.5/AN5/CEX2 8 P1.6/AN6/CEX3 9 P1.7/AN7/CEX4 P3.0/RxD 12 PLCC44 P3.1/TxD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ P1.4/AN4/CEX1 1 P1.5/AN5/CEX2 2 P1.6/AN6/CEX3 3 P1.7/AN7/CEX4 4 ...
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Table 1. Pin Description Pin Name Type Description VSS GND Circuit ground VCC Supply Voltage VAREF Reference Voltage for ADC VAGND Reference Ground for ADC P0.0:7 I/O Port 8-bit open drain bi-directional I/O port. Port 0 pins ...
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Table 1. Pin Description (Continued) Pin Name Type Description P3.0:7 I/O Port 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and ...
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I/O Configurations Port 1, Port 3 and Port 4 Port 0 and Port 2 A/T89C51AC2 6 Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates ...
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Read-Modify-Write Instructions 4127H–8051–02/08 Figure 2. Port 0 Structure ADDRESS LOW/ DATA READ LATCH INTERNAL BUS D Q P0.X LATCH WRITE TO LATCH READ PIN Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data ...
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Quasi-Bidirectional Port Operation A/T89C51AC2 8 Table 2. Read-Modify-Write Instructions Instruction Description ANL logical AND ORL logical OR XRL logical EX-OR JBC jump if bit = 1 and clear bit CPL complement bit INC increment DEC decrement DJNZ decrement and jump ...
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Figure 4. Internal Pull-Up Configurations 2 Osc. PERIODS OUTPUT DATA INPUT DATA READ PIN Note: Port 2 p1 assists the logic-one output for memory bus cycles. VCC VCC VCC p2 p1(1) p3 P1.x P2.x P3.x P4 ...
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SFR Mapping Table 3. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer Data Pointer Low byte DPL 82h LSB of DPTR Data Pointer High byte DPH ...
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Table 5. Timers SFRs (Continued) Mnemonic Add Name Timer/Counter 2 T2CON C8h control Timer/Counter 2 T2MOD C9h Mode Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte Watchdog Timer WDTRST A6h Reset Watchdog Timer WDTPRG ...
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Table 7. PCA SFRs (Continued) Add Name Mnemonic CCAP0L EAh PCA Compare Capture Module 0 L CCAP1L EBh PCA Compare Capture Module 1 L CCAP2L ECh PCA Compare Capture Module 2 L CCAP3L EDh PCA Compare Capture Module 3 L ...
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Table 11. SFR Mapping (1) 0/8 1/9 IPL1 CH F8h xxxx xx0x 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx xx0x 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 00x0 0000 00xx x000 PSW FCON D0h 0000 ...
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Clock Description A/T89C51AC2 14 The A/T89C51AC2 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power ...
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Figure 5. Clock CPU Generation Diagram XTAL1 XTAL2 PD PCON.1 ÷ CKCON.0 4127H–8051–02/08 X2B PCON.0 Hardware byte On RESET IDL X2 CKCON.0 0 ÷ ÷ 2 ÷ ÷ ÷ 1 ...
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Figure 6. Mode Switching Waveforms XTAL1 XTAL1/2 X2 bit CPU clock STD Mode Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a ...
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Register 4127H–8051–02/08 Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register WDX2 PCAX2 Bit Bit Number Mnemonic Description Reserved - - Do not set this bit. Watchdog clock 6 WDX2 Clear to select 6 clock periods ...
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Power Management Two power reduction modes are implemented in the A/T89C51AC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals ...
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Warm Reset To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running. The number of clock periods is mode independent (X2 or X1). Watchdog ...
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Power-down Mode Entering Power-down Mode Exiting Power-down Mode A/T89C51AC2 20 The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited ...
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Figure 9. Power-down Exit Waveform Using INT1:0# INT1:0# OSC Active phase 2. Generate a reset. Notes: Table 14. Pin Conditions in Special Operating Modes 4127H–8051–02/08 Power-down phase Oscillator restart phase – A logic high on the RST pin clears PD ...
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Registers A/T89C51AC2 22 Table 15. PCON Register PCON (S:87h) – Power configuration Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode 1, ...
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Data Memory 4127H–8051–02/08 The A/T89C51AC2 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 1024 ...
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Internal Space Lower 128 Bytes RAM Upper 128 Bytes RAM Expanded RAM A/T89C51AC2 24 The lower 128 Bytes of RAM (see Figure 11) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes ...
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External Space Memory Interface External Bus Cycles 4127H–8051–02/08 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD, WR, and ALE). Figure 13 shows the structure of the external ...
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A/T89C51AC2 26 Figure 14. External Data Read Waveforms CPU Clock ALE DPL Notes: 1. signal may be stretched using M0 bit in AUXR register When executing MOVX @Ri instruction, P2 outputs ...
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Dual Data Pointer Description Application 4127H–8051–02/08 The A/T89C51AC2 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the ...
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Registers A/T89C51AC2 28 Table 18. PSW Register PSW (S:D0h) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 ...
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Bit Bit Number Mnemonic Description Internal/External RAM (00h - FFh) access using MOVX @ Ri/@ DPTR 1 EXTRAM 0 - Internal XRAM access using MOVX @ Ri/@ DPTR External data memory access. Disable/Enable ALE ALE ...
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EEPROM Data Memory Write Data in the Column Latches Programming Read Data A/T89C51AC2 30 The 2 KB on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits ...
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Examples 4127H–8051–02/08 ;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: ; Save and clear EA MOV EECON, ...
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Registers A/T89C51AC2 32 Table 21. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch command bits 7-4 EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. ...
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Program/Code Memory 4127H–8051–02/08 The A/T89C51AC2 implement on-chip program/code memory. Figure 17 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- ...
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External Code Memory Access Memory Interface External Bus Cycles A/T89C51AC2 34 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 18 shows the structure of ...
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Figure 19. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 P2 PCH Flash Memory Architecture Figure 20. Flash Memory Architecture Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) 4127H–8051–02/08 PCL D7:0 PCH A/T89C51AC2 features ...
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FM0 Memory Architecture User Space Extra Row (XRow) Hardware Security Byte Column Latches Cross Flash Memory Access Description A/T89C51AC2 36 The Flash memory is made blocks (see Figure 20): • The memory array (user space ...
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Overview of FM0 Operations Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column Launching Programming 4127H–8051–02/08 The CPU interfaces to the Flash memory through the FCON register and AUXR1 ...
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Status of the Flash Memory Selecting FM1 Loading the Column Latches A/T89C51AC2 38 Table 25. Programming Spaces Write to FCON FPL3:0 FPS User Extra Row Hardware 5 X Security A X Byte ...
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Programming the Flash Spaces User Extra Row 4127H–8051–02/08 Figure 21. Column Latches Loading Procedure Note: The last page address used when loading the column latch is the one used to select the page programming address. The following procedure is used ...
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Hardware Security Byte A/T89C51AC2 40 Figure 22. Flash and Extra Row Programming Procedure Column Latches Loading The following procedure is used to program the Hardware summarized in Figure 23: • Set FPS and map Hardware byte (FCON = 0x0C) • ...
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Reading the Flash Spaces User Extra Row Hardware Security Byte 4127H–8051–02/08 Figure 23. Hardware Programming Procedure Flash Spaces Programming Save and Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, ...
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Flash Protection from Parallel Programming Preventing Flash Corruption A/T89C51AC2 42 Figure 24. Reading Procedure Flash Spaces Reading Flash Spaces Mapping FCON = 0000aa0b DPTR = Address Exec: MOVC A, @A+DPTR Note for the Hardware Security Byte. ...
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Registers 4127H–8051–02/08 FCON RegisterFCON (S:D1h) Flash Control Register FPL3 FPL2 FPL1 Bit Bit Number Mnemonic Description Programming Launch Command Bits 7-4 FPL3:0 Write 5Xh followed by AXh to launch the programming according to FMOD1:0 (see Table 25) ...
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Operation Cross Memory Access Table 27. Cross Memory Access Action RAM Read boot FLASH Write Read FM0 Write External Read memory Write or Code Roll Over Note: 1. RWW: Read While Write A/T89C51AC2 44 Space addressable in ...
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Sharing Instructions 4127H–8051–02/08 Table 28. Instructions shared XRAM EEPROM Action RAM ERAM Read MOV MOVX Write MOV MOVX Note: by cl: using Column Latch Table 29. Read MOVX A, @DPTR EEE bit in FPS in EECON Register FCON Register ENBOOT ...
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Table 31. Read MOVC A, @DPTR FCON Register Code Execution FMOD1 FMOD0 FPS From FM0 From FM1 (ENBOOT = External code : X 0 ...
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In-System With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the A/T89C51AC2 allows the system engineer the development of applica- Programming (ISP) tions with a very high level of flexibility. This flexibility is ...
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Boot Process Software Boot Process Many algorithms can be used for the software boot process. Below are descriptions of Example the different flags and Bytes. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants ...
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Figure 26. Hardware Boot Process Algorithm ENBOOT = 0000h Application in FM0 Application Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All ...
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Hardware Security Byte Table 33. Hardware Security Byte After erasing the chip in parallel mode, the default value is : FFh The erasing in ISP mode (from bootloader) does not modify this byte. Notes: A/T89C51AC2 X2B ...
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Serial I/O Port Figure 27. Serial I/O Port Block Diagram TXD RXD Framing Error Detection Figure 28. Framing Error Block Diagram 4127H–8051–02/08 The A/T89C51AC2 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both ...
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Automatic Address Recognition A/T89C51AC2 52 Figure 29. UART Timing in Mode 1 RXD D0 D1 Start bit RI SMOD0=X FE SMOD0=1 Figure 30. UART Timing in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE ...
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Given Address Broadcast Address 4127H–8051–02/08 Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care ...
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Registers A/T89C51AC2 54 For slaves A and B, bit don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves ...
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Table 35. SADEN Register SADEN (S:B9h) Slave Address Mask Register – – – Bit Bit Number Mnemonic Description 7-0 Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 36. SADDR ...
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A/T89C51AC2 56 Table 38. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 – Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...
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Timers/Counters Timer/Counter Operations Timer 0 4127H–8051–02/08 The A/T89C51AC2 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event ...
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Mode 0 (13-bit Timer) Figure 31. Timer/Counter Mode 0 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 1 (16-bit Timer) Figure 32. Timer/Counter x ...
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Mode 2 (8-bit Timer with Auto- Reload) Figure 33. Timer/Counter Mode 2 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 3 (Two 8-bit Timers) ...
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Timer 1 Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) Interrupt A/T89C51AC2 60 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The ...
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Figure 35. Timer Interrupt System TF0 TCON.5 TF1 TCON.7 Timer 0 Interrupt Request ET0 IEN0.1 Timer 1 Interrupt Request ET1 IEN0.3 61 ...
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Registers A/T89C51AC2 62 Table 39. TCON Register TCON (S:88h) Timer/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag 7 TF1 Cleared by hardware when processor vectors to interrupt routine. Set by ...
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Table 40. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set ...
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A/T89C51AC2 64 Table 41. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register – – – Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0. Reset Value = 0000 0000b Table 42. TL0 Register TL0 ...
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Table 44. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register – – – Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1. Reset Value = 0000 0000b – – ...
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Timer 2 Auto-Reload Mode Figure 36. Auto-Reload Mode Up/Down Counter see section “Clock” FT2 CLOCK T2 A/T89C51AC2 66 The A/T89C51AC2 timer 2 is compatible with timer 2 in the 80C52 16-bit timer/counter: the count is maintained by ...
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Programmable Clock- Output Figure 37. Clock-Out Mode FT2 CLOCK T2 T2EX 4127H–8051–02/08 In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (See Figure 37). The input clock increments TL2 at frequency F repeatedly counts to overflow ...
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Registers A/T89C51AC2 68 Table 45. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 ...
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Table 46. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
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A/T89C51AC2 70 Table 48. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 49. ...
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Watchdog Timer A/T89C51AC2 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s ...
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Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 51. Machine Cycle Count To compute WD Time-Out, the following formula is applied: Note: The following table outlines the time-out ...
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Watchdog Timer During In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of Power-down Mode and exiting Power-down mode: by ...
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A/T89C51AC2 74 Table 54. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register – – – Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register is ...
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Programmable Counter Array (PCA) PCA Timer 4127H–8051–02/08 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves ...
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Figure 39. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle PCA Modules A/T89C51AC2 76 CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit ...
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PCA Interrupt Figure 40. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 PCA Capture Mode 4127H–8051–02/08 Each module in the PCA has a special function register associated with it (CCAPM0 for module 0...). ...
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Figure 41. PCA Capture Mode CEXn 16-bit Software Timer Mode Figure 42. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to ...
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High Speed Output Mode Figure 43. PCA High Speed Output Mode Write to CCAPnH Reset Write to CCAPnL “0” “1” Enable Pulse Width Modulator Mode 4127H–8051–02/08 In this mode the CEX output (on port 1) associated with the PCA module ...
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Figure 44. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) PCA Watchdog Timer A/T89C51AC2 80 CCAPnH CCAPnL 8-Bit Comparator ECOMn PWMn CCAPMn.6 CCAPMn.1 An on-board Watchdog timer is available with ...
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PCA Registers 4127H–8051–02/08 Table 55. CMOD Register CMOD (S:D9h) PCA Counter Mode Register CIDL WDTE - Bit Bit Number Mnemonic Description PCA Counter Idle Control bit 7 CIDL Clear to let the PCA run during Idle mode. ...
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A/T89C51AC2 82 Table 56. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Bit Number Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA ...
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Table 57. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0.. CCAPnH 7 CCAPnH 6 CCAPnH 5 Bit Bit Number Mnemonic Description CCAPnH 7:0 High ...
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A/T89C51AC2 84 Table 59. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Bit Number Mnemonic Description Reserved 7 - The Value read ...
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Table 60. CH Register CH (S:F9h) PCA Counter Register High Value Bit Bit Number Mnemonic Description 7:0 CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 61. ...
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Analog-to-Digital Converter (ADC) Features ADC Port 1 I/O Functions VAREF A/T89C51AC2 86 This section describes the on-chip 10 bit analog-to-digital converter of the A/T89C51AC2. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog ...
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Figure 45. ADC Description ADC CLOCK AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 111 SCH2 SCH1 ADCON.2 ADCON.1 Figure 46. Timing Diagram CLK ADEN (1) T SETUP ADSST ADEOC Notes: 1. Tsetup ...
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ADC Converter Operation Voltage Conversion Clock Selection A/T89C51AC2 88 A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) ...
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Figure 47. A/D Converter clock CPU CLOCK CPU Core Clock Symbol ADC Standby Mode IT ADC Management Routines examples 4127H–8051–02/08 Prescaler ADCLK ÷ 2 When the ADC is not used possible to set it in standby mode by ...
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A/T89C51AC2 90 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt 4127H–8051–02/08 ...
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Registers 4127H–8051–02/08 Table 63. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 7-0 CH 0:7 Set to use P1.x as ADC input. Clear to use P1.x ...
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A/T89C51AC2 92 Table 65. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved 7-5 - The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler ...
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Interrupt System Introduction Figure 49. Interrupt Control System External INT0# Interrupt 0 Timer 0 External INT1# Interrupt 1 Timer 1 CEX0:5 PCA TxD UART RxD Timer AIN1:0 Converter 4127H–8051–02/08 The controller has a total of 8 ...
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A/T89C51AC2 94 Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all ...
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Registers 4127H–8051–02/08 Table 70. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If EA=1, ...
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A/T89C51AC2 96 Table 71. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 ...
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Table 72. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority ...
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A/T89C51AC2 98 Table 73. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Table 74. IPH0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt ...
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A/T89C51AC2 100 Table 75. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Electrical Characteristics Absolute Maximum Ratings* Ambiant Temperature Under Bias industrial ....................................................... -40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage on V from V ......................................-0. Voltage on Any Pin from V ...
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A/T89C51AC2 102 Notes: 1. Operating I is measured with all output pins disconnected; XTAL1 driven with (see Figure 53.), V CLCH CHCL 0.5V; XTAL2 N.C RST = ...
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Figure 51. I Figure 52. I Figure 53. Clock Signal Waveform for I 4127H–8051–02/08 Test Condition, Idle Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Test Condition, Power-Down ...
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DC Parameters for A/D Converter Table 77. DC Parameters for AD Converter in Precision Conversion Symbol Parameter AVin Analog input voltage (2) Rref Resistance between Vref and Vss Vref Reference voltage Cai Analog input Capacitance Rai Analog input Resistor INL ...
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External Program Memory Table 78. Symbol Description Characteristics Table 79. AC Parameters for a Fix Clock ( MHz) 4127H–8051–02/08 Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address ...
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External Program Memory Read Cycle T ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 A/T89C51AC2 106 Table 80. AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max ...
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External Data Memory Table 81. Symbol Description Characteristics Table 82. AC Parameters for a Variable Clock ( MHz) 4127H–8051–02/08 Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV ...
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A/T89C51AC2 108 Table 83. AC Parameters for a Variable Clock Symbol Type T Min RLRH T Min WLWH T Max RLDV T Min RHDX T Max RHDZ T Max LLDV T Max AVDV T Min LLWL T Max LLWL T ...
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External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing – Shift Register Mode Table 84. Symbol ...
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Shift Register Timing Waveforms INSTRUCTION ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Characteristics (XTAL1) A/T89C51AC2 110 Table 85. AC Parameters for a Fix Clock ( MHz) Symbol T XLXL T QVHX ...
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External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at V Timing measurement are made at V Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from ...
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Clock Waveforms STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST ...
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Flash/EEPROM Memory Table 88. Timing Symbol Definitions Table 89. Memory AC Timing VDD = 5V Figure 54. Flash Memory – ISP Waveforms Figure 55. Flash Memory – Internal Busy Waveforms A/D Converter Table 90. AC Parameters for A/D Conversion 4127H–8051–02/08 ...
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... Ordering Information Table 91. Possible Order Entries Part Number Supply Voltage T89C51AC2-RLTIM T89C51AC2-SLSIM AT89C51AC2-RLTUM 3V to 5.5V + 10% AT89C51AC2-SLSUM A/T89C51AC2 114 Temperature Range Max Frequency OBSOLETE Industrial & Green 40 MHz Package Packing VQFP44 Tray PLCC44 Stick 4127H–8051–02/08 ...
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Package Drawings VQFP44 4127H–8051–02/08 115 ...
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PLCC44 A/T89C51AC2 116 4127H–8051–02/08 ...
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Datasheet Change Log for A/T89C51AC2 Changes from 4127D - 02/03 to 4127E - 01/05 Changes from 4127E - 01/05 to 4127F - 03/05 Changes from 4127F - 03/05 to 4127G - 05/06 Changes from 4127G - 05/06 to 4127H - ...
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Table of Contents Features................................................................................................. 1 Description............................................................................................ 1 Block Diagram ...................................................................................... 2 Pin Configuration ................................................................................. 3 I/O Configurations................................................................................................. 6 Port 1, Port 3 and Port 4 ....................................................................................... 6 Port 0 and Port 2................................................................................................... 6 Read-Modify-Write Instructions ............................................................................ 7 Quasi-Bidirectional Port Operation ...
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Registers............................................................................................................. 43 Operation Cross Memory Access ..................................................... 44 Sharing Instructions........................................................................... 45 In-System Programming (ISP)........................................................... 47 Flash Programming and Erasure........................................................................ 47 Boot Process ...................................................................................................... 48 Application Programming Interface..................................................................... 49 XROW Bytes....................................................................................................... 49 Hardware Security Byte ...................................................................................... 50 Serial I/O Port...................................................................................... 51 ...
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Analog-to-Digital Converter (ADC) ................................................... 86 Features.............................................................................................................. 86 ADC Port 1 I/O Functions ................................................................................... 86 VAREF................................................................................................................ 86 ADC Converter Operation................................................................................... 88 Voltage Conversion ............................................................................................ 88 Clock Selection ................................................................................................... 88 ADC Standby Mode ............................................................................................ 89 IT ADC Management .......................................................................................... 89 Routines examples ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. © Atmel Corporation 2008. All rights reserved. Atmel tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...