AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 21

• Manufacturer Part Number: AT89C51CC01
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC01

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 1.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

Figure 9. Power-down Exit Waveform Using INT1:0#
4129N–CAN–03/08
INT1:0#
OSC
Active phase
2. Generate a reset.
Notes:
Table 14. Pin Conditions in Special Operating Modes
Down(inter
nal code)
(external
(external
(internal
Power-
Power-
Mode
Reset
code)
code)
Down
code)
Idle
Idle
–
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the T89C51CC01 and vectors
the CPU to address 0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
3.
Power-down phase
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
RAM content.
Floating
Floating
Floating
Port 0
Data
Data
Port 1
High
Data
Data
Data
Data
Oscillator restart phase
Port 2
High
Data
Data
Data
Data
Port 3
High
Data
Data
Data
Data
Port 4
Active phase
High
Data
Data
Data
Data
ALE
High
High
High
Low
Low
PSEN#
High
High
High
Low
Low
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