AT89LP4052 Atmel Corporation, AT89LP4052 Datasheet
AT89LP4052
Manufacturer Part Number
AT89LP4052
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP4052
Flash (kbytes)
4 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
15
Spi
1
Uart
1
Sram (kbytes)
0.25
Operating Voltage (vcc)
2.4 to 5.5
Timers
2
Isp
SPI
Watchdog
Yes
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Errata
The following are known problems with Rev. C of the AT89LP2052/LP4052 device:
1. JBC to TF0, TF1, IE0, IE1, RI, TI
JBC may cause a loss of interrupt information if used with any interrupt flag. Therefore
JBC should not be used to poll for interrupt flags.
2. Read-Modify-Write to ACSR (ANL, ORL, XRL)
Read-Modify-Write (RMW) instructions may cause a loss of Comparator interrupt
information if used with any bit in ACSR, i.e. the RMW instructions need to be treated
as a direct move to ACSR such as MOV ACSR,#IMM. These instructions may be
used when it is not possible for the interrupt to occur at the same time as the instruc-
tion is being executed, which means in the following circumstances:
3. Read-Modify-Write to TCON (SETB, CLR, CPL, ANL, ORL, XRL)
Read-Modify-Write instructions may cause a loss of external interrupt information if
used with TCON. These instructions may be used when it is not possible for the exter-
nal interrupt to occur at the same time as the instruction is being executed, which
means in the following circumstances:
3. Interrupt Recovery from Power-down Mode
When attempting interrupt recovery from power-down, the external interrupt pins INT0
(P3.2) and INT1 (P3.3) should not transition low until at least 10 µs after entry into
power-down. If the pins are low immediately before entering power-down, or go low
while attempting to enter power-down, the device can get stuck in a power-down-like
state requiring a power cycling sequence to wake up.
A. The Comparator is not active, or
B. Within a short period of time after CF is set, or
C. The flag is level-sensitive and the input condition will last through the next
D. Any time if the application can afford to miss an edge event. The actual miss
A. Any time if not using external interrupts or if the interrupts are level sensitive,
B. If using a single edge-triggered interrupt, within a short time after the flag is
C. Any time if the application can afford to miss an edge event. The actual miss
POLL: JBC FLAG, NEXT
should be replaced by:
POLL: JNB FLAG, POLL
Problem Fix/Workaround:
instruction, or
frequency will depend on the application code.
or
set, or
frequency will depend on the application code.
SJMP POLL
CLR FLAG
SJMP NEXT
AT89
Microcontrollers
AT89LP2052
AT89LP4052
Rev. C
Errata Sheet
3570B–MICRO–6/05
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AT89LP4052 Summary of contents
Page 1
... INT1 (P3.3) should not transition low until at least 10 µs after entry into power-down. If the pins are low immediately before entering power-down low while attempting to enter power-down, the device can get stuck in a power-down-like state requiring a power cycling sequence to wake up. AT89 Microcontrollers AT89LP2052 AT89LP4052 Rev. C Errata Sheet 3570B–MICRO–6/05 ...
Page 2
... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...