ATmega406 Atmel Corporation, ATmega406 Datasheet
ATmega406
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... Packages – 48-pin LQFP • Operating Voltage: 4.0 - 25V • Maximum Withstand Voltage (High-voltage pins): 28V • Temperature Range: -30°C to 85°C – Speed Grade: 1 MHz ® 8-bit Microcontroller 8-bit Microcontroller with 40K Bytes In-System Programmable Flash ATmega406 Preliminary 2548E–AVR–07/06 ...
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... Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATmega406 2 Pinout ATmega406. Top View SGND 1 (ADC0 /PCINT0 ) PA0 2 (ADC1 /PCINT1 ) PA1 ...
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... Overview The ATmega406 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega406 achieves throughputs approaching 1 MIPS at 1 MHz. 2.1 Block Diagram Figure 2-1. Block Diagram XTAL1 Oscillator Circuits / Clock Generation XTAL2 Watchdog ...
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... Cell Balancing FETs, and a voltage regulator on a monolithic chip, the Atmel ATmega406 is a powerful microcontroller that provides a highly flexible and cost effective solution for Li-ion Smart Battery applications. The ATmega406 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-chip Debugger. ...
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... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega406 as listed in nate Functions of Port A” on page 2.2.9 ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega406 as listed in nate Functions of Port D” on page 2.2.12 SCL SMBUS clock, Open Drain bidirectional pin ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 2548E–AVR–07/06 ATmega406 7 ...
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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. ATmega406 8 Block Diagram of the AVR Architecture ...
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... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega406 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the ”AVR Instruction Set” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the ”AVR Instruction Set” for detailed information. ATmega406 ...
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... Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 5-2, each register is also assigned a data memory address, mapping them ATmega406 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. ATmega406 12 The X-, Y-, and Z-registers 15 ...
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... Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back ATmega406 SP12 SP11 SP10 SP9 SP4 ...
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... This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the ATmega406 14 for details. for more information. The Reset Vector can also be moved to the start of 178. ” ...
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... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2548E–AVR–07/06 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set Global Interrupt Enable ATmega406 15 ...
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... AVR Memories This section describes the different memories in the ATmega406. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega406 features an EEPROM Memory for data storage. All three memory spaces are linear and regular ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2,048 bytes of internal data SRAM in the ATmega406 are all accessible through all these addressing modes. The Register File is described in 11. ...
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... EEPROM Data Memory The ATmega406 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... Read/Write Initial Value • Bits 15:9 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bits 8:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...
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... EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. ATmega406 20 EEPROM Mode Bits Programming ...
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... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 2548E–AVR–07/06 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATmega406 Table 6-2 lists the typical pro- Typ Programming Time 3 ...
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... EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. ATmega406 22 ; 2548E–AVR–07/06 ...
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... Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; ATmega406 23 ...
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... I/O Memory The I/O space definition of the ATmega406 is shown in All ATmega406 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions ...
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... CPU AVR Clock Control Battery Protection Watchdog Timer Reset Logic & FET Control Ultra Low Power RC Oscillator clock when TWI communication is not used. Note that address TWI ATmega406 ”Power Manage- Other I/O Coulomb Counter TWI Modules ADC clk VADC clk clk clk ...
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... The start-up times for the Fast RC Oscillator are determined by the SUT Fuses as shown in Table 7-1 on page Table 7-1. SUT1:0 Note: ATmega406 26 VADC CCADC 26. Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power-down and Power-save ...
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... The Ultra Low Power RC Oscillator is used for tim- ing this real-time part of the start-up time. Start-up times are determined by the SUT Fuses as 2548E–AVR–07/06 32 kHz Crystal Oscillator Connections C2 C1 Table 10-1 on page ATmega406 Figure 7-2. This Oscillator is optimized for XTAL2 XTAL1 GND ”Calibration Bytes” on page 50 ...
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... If the CPU detects that the crystal clock is not operating correctly, it can switch to the Slow RC Oscillator as a less accurate, but still func- tional, backup solution. ATmega406 28 Table 7-2. The number of Ultra Low Power RC Oscillator cycles used for each time-out Table 7-3 ...
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... Read/Write Initial Value • Bits 7:2 - Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 1 - XOE: 32 kHz Crystal Oscillator Enable The XOE bit is used to enable the 32 kHz Crystal Oscillator before it is selected as clock source. ...
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... Switch to the RC Oscillator by clearing the ACS bit (zero) while keeping the XOE bit set (one). 2. Disable the Crystal Oscillator by clearing the XOE bit (zero) while keeping the ACS bit cleared (zero). ATmega406 30 Asynchronous Clock Source and Oscillator Enable Conditions 32 kHz Crystal ...
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... Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega406, and will always read as zero. • Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0 These bits select between the five available sleep modes as shown in Table 8-1 ...
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... When waking up from Power-save mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined in ATmega406 32 and clk , while allowing the other clocks to run. Idle mode enables the ...
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... External Interrupts (2) CBP VBP WDT 2548E–AVR–07/06 56. Active modules in different Sleep Modes Active Idle ATmega406 ”External Interrupts” ”Clock Sources” on page 26. Mode ADC Power- Power- NRM save down (1) (1) X ...
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... Note: Table 8-3. Mode Idle ADC NRM Power-save Power-down Power-off The sleep mode state diagram is shown in ATmega406 34 Active modules in different Sleep Modes (Continued) Active Idle Address Match and Bus Connect/Disconnect Wake-up only. 2. When Discharge-FET is switched off, Short-circuit Protection is automatically disabled to reduce current consumption. ...
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... Sleep Mode State Diagram Interrupt Sleep ADC NRM Deep Under-voltage 2548E–AVR–07/06 Reset From all States RESET Reset Time-out Active Sleep Interrupt Idle Sleep or Deep Under-voltage Deep Under-voltage Power-off Charger Connected Regulator-on ATmega406 Interrupt Interrupt Sleep Sleep Power-save Power-down Deep Deep Under-voltage Under-voltage 35 ...
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... Read/Write Initial Value • Bit 7:4 - Res: Reserved bits These bits are reserved in ATmega406 and will always read as zero. • Bit 3 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation. ...
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... Digital REG ”BPCR – Battery Protection Control Register” on page ”Voltage ADC – 10-channel General Purpose 12-bit Sigma-Delta ADC” on page ATmega406 ”Watchdog Timer” ) are stopped, the input buffers of the device will for details on which pins are for details ...
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... If enabled, the CC-ADC will consume power independent of sleep mode. To save power, the CC-ADC should be disabled when not used, and before entering Power-down sleep mode. See ”Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC” on page 106 ADC operation. ATmega406 38 for details on CC- 2548E–AVR–07/06 ...
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... The time-out period of the delay counter is defined by the user through the SUT Fuses. The dif- ferent selections for the delay period are presented in 9.2 Reset Sources The ATmega406 has several reset sources: • Power-on Reset. If the chip is in Power-off mode, the Charger Detect module generates a reset pulse when a charger is connected.See for details. ...
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... To be able to start from power-off, a charger must be detected. In order to detect a charger, the voltage at the BATT pin must rise above the Charger-on Threshold Voltage level,V issue a Power- on Reset (POR), and the chip enters RESET mode. When the Delay Counter times out, the chip will enter Active mode. characteristics. ATmega406 40 Reset Logic V REG ...
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... Power-on Reset in Operation. V COT V BATT POR TIMEOUT Power-off Table 30-3 on page RST – has expired. TOUT External Reset During Operation FET ATmega406 t TOUT Reset 230) will generate a reset, even if the clock is not – on its positive edge, the delay counter starts the Active 41 ...
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... Figure 9-4. 9.2.4 Brown-out Detection ATmega406 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VREG level during operation by comparing fixed trigger level V teresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V The BOD is automatically enabled in all modes of operation, except in Power-off mode. ...
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... Watchdog Timer ATmega406 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 9-6 ...
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... MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); } Note: ATmega406 44 (1) r16, MCUSR r16, (0xff & (0<<WDRF)) MCUSR, r16 r16, WDTCSR r16, (1<<WDCE) | (1<<WDE) WDTCSR, r16 r16, (0< ...
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... WDTCSR, r16 ; -- Finished setting new values, used 2 cycles - ; Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. ”About Code Examples” on page ATmega406 7. 45 ...
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... Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega406, and will always read as zero. • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET ...
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... Watchdog Timer Configuration WDE WDIE Mode 0 0 Stopped 0 1 Interrupt Mode 1 0 System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode ATmega406 WDE WDP2 WDP1 WDP0 R/W R/W R/W R Action on Time-out None Interrupt Reset Interrupt, then go to System ...
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... The different prescaling values and their corresponding Timeout Periods are shown in Table 9-2.. Table 9-2. WDP3 ATmega406 48 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 ...
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... Wake-up Timer The following section describes the Wake-up Timer in the ATmega406. • One Wake-up Timer Interrupt • 8 Selectable Time-out Periods • Separate Wake-up Timer Calibration Flag • Separate Clock Source 10.1 Overview The Wake-up Timer is clocked either from the Slow RC Oscillator or from the external 32 kHz crystal oscillator ...
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... ATmega406 50 Table 10-1. The Wake-up Timer should always be reset when changing Number of Slow RC Number of 32kHz Crystal Oscillator Cycles Oscillator Cycles 4K(4096) 1K(1024) 8K(8192) 2K(2048) 16K(16384) 4K(4096) 32K(32768) 8K(8192) 64K(65536) 16K(16384) 128K(131072) 32K(32768) ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega406. For a general explanation of the AVR interrupt handling, refer to page 14. 11.1 Interrupt Vectors in ATmega406 Table 11-1. Vector No Notes: Table 11-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt 2548E– ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega406 is: Address Labels Code 0x0000 jmp RESET 0x0002 jmp BPINT ...
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... Store Program Memory Ready Handler r16,high(RAMEND); Main program start SPH,r16 ; Set Stack Pointer to top of RAM r16,low(RAMEND) SPL,r16 ; Enable interrupts xxx Comments RESET ; Reset handler BPINT ; Battery Protection Interrupt Handler EXT_INT0 ; External Interrupt Request 0 Handler ... ; SPM_RDY ; Store Program Memory Ready Handler r16,high(RAMEND); Main program start ATmega406 53 ...
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... Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret C Code Example void Move_interrupts(void Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); } ATmega406 54 SPH,r16 ; Set Stack Pointer to top of RAM r16,low(RAMEND) SPL,r16 ; Enable interrupts xxx 2548E–AVR–07/06 ...
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... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 178 ATmega406 ...
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... Therefore recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Regis- ter before the interrupt is re-enabled. ATmega406 ...
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... Initial Value • Bits 7:4 – RES: Reserved Bits These bits are reserved bits ins the ATmega406, and will always read as zero. • Bits 3:0 – INT3 - INT0: External Interrupt Request Enable When an INT3 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Register – ...
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... Initial Value • Bit 7:2 - Res: Reserved Bits These bits are reserved bits in the ATmega406, and will always read as zero. • Bit 1 - PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled ...
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... I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 2548E–AVR–07/ PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega406 PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK1 PCMSK0 ...
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... How each alternate function interferes with the port pin is described in full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATmega406 60 Figure 13-1 on page 60. Refer to Pxn ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 73, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega406 ( DDxn Q CLR RESET ...
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... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t ATmega406 62 summarizes the control signals for the pin value. Port Pin Configurations ...
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... SYNC LATCH PINxn r17 Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega406 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx 0x00 ...
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... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. ATmega406 64 (1) r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17,(1< ...
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... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. 2548E–AVR–07/06 or GND is not recommended, since this may cause excessive currents if the pin is CC ATmega406 65 ...
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... Figure 13-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: ATmega406 66 shows how the port pin control signals from the simplified (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATmega406 Fig- 67 ...
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... MCU. • ADC3:0/PCINT3:0 – Port A, Bit 3:0 Analog to Digital Converter, Channels 3:0. PCINT3 - PCINT0, Pin Change Interrupt Sources 3:0. The PA3:0 pins can serve as external interrupt sources to the MCU. ATmega406 68 Port A Pins Alternate Functions Port Pin Alternate Function INT3 (External Interrupt 3) ...
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... PCINT2 – – PCINT3 INPUT PCINT2 INPUT ADC3 INPUT ADC2 INPUT ATmega406 PA5/INT1/ PA4/ADC4 PCINT5 INT0/PCINT4 – – INT1 ENABLE INT0 ENABLE INT1 ENABLE INT0 ENABLE INT1 INPUT/ ...
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... TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG Interface is enabled, this pin can not be used as an I/O pin. PCINT11, Pin Change Interrupt Source 11. The PB3 pin can serve as external interrupt source to the MCU. ATmega406 70 Port B Pins Alternate Functions Alternate Functions ...
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... PCINT15 PCINT14 OC0B Enable OC0A Enable OC0B OC0A – – PCINT15 INPUT PCINT14 INPUT – – ATmega406 PB5/ PB4/ PCINT13 PCINT12 – – PCINT13 INPUT PCINT12 INPUT – ...
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... The Port D pins with alternate functions are shown in Table 13-9. Port Pin PD0 The alternate pin configuration is as follows: • T0 – Port B, Bit 0 T0, Timer/Counter0 Counter Source. Table 13-10 on page 73 in Figure 13-5 on page ATmega406 72 Overriding Signals for Alternate Functions in PB3:PB0 PB3/TCK/ PB2/TMS/ PCINT11 PCINT10 JTAGEN JTAGEN 1 ...
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... PORTA4 R/W R/W R/W R DDA7 DDA6 DDA5 DDA4 R/W R/W R/W R PINA7 PINA6 PINA5 PINA4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega406 PD0/ – Input – – – IVSEL IVCE R R R/W R PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R/W ...
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... PORTD – Port D Data Register Bit 0x0B (0x2B) Read/Write Initial Value 13.4.9 DDRD – Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 13.4.10 PIND – Port D Input Pins Address Bit 0x09 (0x29) Read/Write Initial Value ATmega406 PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R ...
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... Pxn. 2548E–AVR–07/06 for a complete list of parameters. Pxn C pin 76. 75. ATmega406 Figure 14-1. See ”Electrical Characteris- Logic See Figure "General High Voltage Digital I/O" for Details ”Register Description for High Voltage Output Ports” ...
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... Register Description for High Voltage Output Ports 14.3.1 PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value ATmega406 76 Pxn WRx: WRITE PORTx RRx: READ PORTx REGISTER 1. WRx and RRx are common to all pins within the same port. 76, the PORTxn bits are accessed at the PORTx I/O address. If PORTxn ...
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... Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. 2548E–AVR–07/06 ”Pinout ATmega406.” on page ”8-bit Timer/Counter Register Description” on page ”PRR0 – Power Reduction Register 0” on page 36 Count ...
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... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): ATmega406 78 Table 15-1 are also used extensively throughout the document. Definitions The counter reaches the BOTTOM when it becomes 0x00. ...
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... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 82. shows a block diagram of the Output Compare unit. ATmega406 in the following. T0 (”Modes of Operation” on page 82). ”Modes of 79 ...
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... Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- ATmega406 80 DATA BUS OCRnx ...
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... PWM refer to 2548E–AVR–07/06 COMnx1 Waveform COMnx0 D Generator FOCn D PORT D clk I/O See Section “15.8” on page 88. Table 15-2 on page ATmega406 Figure 15-4 shows a simplified Q 1 OCnx OCnx DDR 88. For fast PWM mode, refer to Table 15-4 on page 89. Pin Table 15-3 on ...
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... This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. ATmega406 82 81.). ”Timer/Counter Timing Diagrams” on page Figure 15-5 ...
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... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 2548E–AVR–07/ clk_I ------------------------------------------------- - ⋅ ⋅ ( OCnx OCRnx ATmega406 OCnx Interrupt Flag Set (COMnx1 OC0 ) 83 = ...
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... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f ATmega406 84 Figure 15-6. The TCNT0 value is in the timing diagram shown as a his- ...
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... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 2548E–AVR–07/06 15-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 ATmega406 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
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... MAX value in all modes other than phase correct PWM mode. Figure 15-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 15-9 ATmega406 86 Table 15-7 on page f OCnxPCPWM Figure 15-7 Figure 15-8 contains timing data for basic Timer/Counter operation. The figure I/O ...
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... OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega406 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
Page 88
... WGM02:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 15-2. COM0A1 Table 15-3 mode. Table 15-3. COM0A1 Note: ATmega406 COM0A1 COM0A0 COM0B1 R/W R/W R Table 15-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode ...
Page 89
... Set OC0B on Compare Match, clear OC0B at TOP 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. ATmega406 (1) ”Phase Correct PWM Mode” on (1) ” ...
Page 90
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 91
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. 2548E– ...
Page 92
... Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. ATmega406 92 Clock Select Bit Description Description CS01 CS00 ...
Page 93
... Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 94
... Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...
Page 95
... However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. The physical I/O reg- ister and bit locations for ATmega406 are listed in the Description” on page A simplified block diagram of the 16-bit Timer/Counter is shown in I/O registers, including I/O bits and I/O pins, are shown in bold ...
Page 96
... Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code ATmega406 96 (1) (1) 1. See ” ...
Page 97
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See ”About Code Examples” on page ATmega406 7. 97 ...
Page 98
... The Timer/Counter is clocked by an internal clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS1[2:0]) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega406 98 (1) (1) 1. See ” ...
Page 99
... TCNTnL (8-bit) TCNTn (16-bit Counter) Increment TCNT1 by 1. Clear TCNT1 (set all bits to zero). Timer/Counter clock The clk is generated from an internal clock source, selected by the Clock Select ATmega406 TOVn (Int.Req.) Count clk Tn Control Logic Clear is present or not ...
Page 100
... Initial Value • Bit 7:4 – Res: Reserved Bits These bits is a reserved bit in the ATmega406 and always reads as zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to 0x00 in the CPU clock cycle after a compare match ...
Page 101
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R ATmega406 R/W R/W R/W R R/W R/W R/W R TCNT1H TCNT1L OCR1AH OCR1AL 101 ...
Page 102
... Initial Value • Bit 7:2 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and always reads as zero. • Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 103
... CLK_I/O CLK_I/O CLK_I/O pulse for each positive (CSn2 negative (CSn2 clk I/O Synchronization ATmega406 for Timer/Counter0 settings and /128, f /256 /1024. CLK_I/O CLK_I/O Figure 17-1 shows a functional ). The latch is transparent in the clk I Edge Detector Tn_sync ...
Page 104
... Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1 PSRSYNC Note: ATmega406 104 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ...
Page 105
... TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 2548E–AVR–07/ TSM – – – R ATmega406 – – – PSRSYNC R GTCCR 105 ...
Page 106
... Interrupt on Regular Current with Programmable Compare Level and Programmable Sampling Interval: 250/500/1000/2000 ms ATmega406 features a dedicated Sigma-Delta ADC (CC-ADC) optimized for Coulomb Counting to sample the charge or discharge current flowing through the external sense resistor R Two different output values are provided, Instantaneous Current and Accumulate Current. The Instantaneous Current Output has a short conversion time at the cost of lower resolution ...
Page 107
... DATA4 will be lost because DATA3 reading is not completed within the limited period. 2548E–AVR–07/06 . Enable ~12 ms settling Setting of Digital Filters Figure 18-3 on page 108 ATmega406 Figure 18-2 3.9 ms 3.9 ms 7.8 ms DATA1 DATA2 DATA 3 DATA5 shows an Accumulation Current conver- ...
Page 108
... CC-ADC offset value can be found by performing a CC-ADC conversion at typical temperature with zero current flowing through R When the battery is not used or the current level stays very low for a long time recom- mended to estimate the charge flow instead of using the CC-ADC for Coloumb Counting. The ATmega406 108 Enable Setting of Digital Filters ...
Page 109
... Bandgap Calibration C Register” on page • Bit 6 – Res: Reserved This bit is reserved bit in the ATmega406 and will always read as zero. • Bit 5 - CADUB: CC-ADC Update Busy The CC-ADC operates in a different clock domain than the CPU. Whenever a new value is writ- ten to CADCSRA, CADRCC or CADRDC, this value must be synchronized to the CC-ADC clock domain ...
Page 110
... Initial Value • Bits 7, 3 – Res: Reserved These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 6 – CADACIE: CC-ADC Accumulate Current Interrupt Enable When the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled. • ...
Page 111
... CADAC[31:24] CADAC[23:16] CADAC[15:8] CADAC[7: ATmega406 ...
Page 112
... Regular Discharge Current level, the CC-ADC Regular Current Interrupt Flag is set. The value in this register is specified in 2's complement format, and it defines the eight least sig- nificant bits of the Regular Discharge Current level. The most significant bits of the Regular ATmega406 112 7 6 ...
Page 113
... The CC-ADC Regular Discharge Current Register does not affect the setting of the CC-ADC Conversion Complete Interrupt Flag. 2548E–AVR–07/06 Table 18-4. Programmable Range for the Regular Discharge Current Level mΩ SENSE mΩ SENSE ATmega406 Minimum Maximum 0 13700 0 2740 0 1957 Step Size 53.7 10.7 7 ...
Page 114
... Operating Voltage Range 4.0 - 25V. • Fixed Output Voltage at 3.3V. ATmega406 is supplied by the VFET terminal. Operating voltage range at the VFET terminal is 4.0 - 25V. The Internal Voltage Regulator regulates this voltage down to 3.3V, which is a suitable supply voltage for the internal logic, I/O lines, and analog circuitry. ...
Page 115
... After powering-up the regulator the chip will enter Power-off sleep mode (lowest power con- sumption). Until a charger is detected, the chip will stay in this mode. For details on Charger Detect, see Table 30-2 on page 230 2548E–AVR–07/06 ”Power-on Reset and Charger Connect” on page shows the characteristics for powering-up the LDO. ATmega406 40. 115 ...
Page 116
... Pre-scaling of Cell Voltages and VREG • Interrupt on V-ADC Conversion Complete The ATmega406 features a 12-bit Sigma-Delta ADC. Automatic offset cancellation technique reduces the input offset voltage to less than 0.5 mV. The Voltage ADC (V-ADC) is connected to ten different sources through the Input Multiplexer. There are four differential channels for Cell Voltage measurements. These channels are scaled ...
Page 117
... MUX NV Note: The shaded signals are scaled by 0.2, other signals are scaled by 1.0 519 us Interrupt OLD DATA INVALID DATA ATmega406 V-ADC CONVERSION COMPLETE IRQ 8-BIT DATA BUS V-ADC MULTIPLEXER V-ADC CONTROL AND SEL. REG (VADMUX) STATUS REG (VADCSR) V-ADC CONTROL 12-BIT V-ADC DATA REGISTER ...
Page 118
... Bit (0x7C) Read/Write Initial Value • Bit 7:4 – RES: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 3:0 – VADMUX3:0: V-ADC Channel Selection Bits The VADMUX bits determine the V-ADC channel selection. See Table 20-1. 20.3.2 VADCSR – ...
Page 119
... Signature Row from Software” on page 189 ⋅ cell result cell gain calibration word ( ) n n Cell voltage mV = --------------------------------------------------------------------------------------------------- n TBD for details. The absolute temperature in Kelvin is given by: V result VPTAT calibration word temp T(K) = ----------------------------------------------------------------------------------------------- - ATmega406 – VADC[11:8] VADC[7: ...
Page 120
... The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the VADC3:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATmega406 120 7 ...
Page 121
... This voltage reference source is not available for the V-ADC and CC-ADC. ATmega406 has an On-chip temperature sensor for monitoring the die temperature. A voltage Proportional-To-Absolute-Temperature, V connected to the multiplexer at the V-ADC input. This temperature sensor can be used for runt- ime compensation of temperature drift in both the voltage reference and the On-chip Oscillator ...
Page 122
... BOD-reset is issued when calibration is done recommended to change the values of the BGCC and BGCR bits stepwise, with a step size of 1, and with a hold-off time between each step. The hold-off time depends on the size of the voltage regulators external decoupling capacitor. For details, see Table 21-1. ATmega406 122 1.1V BG Reference VPTAT Table 21-1 ...
Page 123
... Read/Write Initial Value • Bit 7 - BGEN This bit is not available from revision E and on of the ATmega406. A complete description is found in the revision A of this document. • Bit 6 – Res: Reserved Bit This bit is reserved for future use. • Bit 5:0 – BGCC5:0: BG Calibration of PTAT Current These bits are used for trimming of the nominal value of the bandgap reference voltage ...
Page 124
... Figure 21-2. Illustration of VREF as a function of temperature. 1.5 0.5 ATmega406 124 Temperature range of interest 1 0 -40 -20 0 BGCRR is used to move the top of the VREF curve to the center of the tempearture range of interest Temperature [ o C] 100 2548E–AVR–07/06 ...
Page 125
... Protection is never automatically disabled when any of the C-FET or PC-FETs are con- trolled by PWM. 2548E–AVR–07/06 C-FET D-FET PC-FET Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled ATmega406 Table 22-1. Cell Balancing FETs MCU Disabled Power-off Operational Operational Operational Operational Operational Operational 125 ...
Page 126
... The application software must then set the DFE and CFE bits in the FET Control and Status Register to re-enable normal operation. If the C-FET is re-enabled and the charger continues to supply too high currents, the Charge Over-current Protection will be activated again. ATmega406 126 ”Register Description for Battery Protection” on page 128 for register descriptions. ...
Page 127
... Description for Battery Protection” on page 128 Battery Protection Parameter Lock LOCK? LOCK? Register Battery Protection Battery Protection Level Register Timing Register PPI NNI Protection VFET Protection ATmega406 for register descriptions. Figure 22-1. 8-BIT DATA BUS LOCK? 8 Interrupt / Request Battery Protection Interrupt Control Register Acknowledge Current ...
Page 128
... Read/Write Initial Value • Bit 7:2 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 1 – BPPLE: Battery Protection Parameter Lock Enable • Bit 0 – BPPL: Battery Protection Parameter Lock The Battery Protection parameters set in the Battery Protection Parameter Registers and the disable function set in the Battery Protection Disable Register can be locked from any further software updates ...
Page 129
... OCPT[3:0] with Corresponding Over-current Delay Time Over-current Protection Reaction Time Typ OCPT[3:0] Typ 1 ms 0100 0101 0110 0111 14 ms ATmega406 OCPT[3:0] R/W R/W R/W R Table 22-2. SCPT[3:0] Typ SCPT[3:0] 1000 610 µ ...
Page 130
... Read/Write Initial Value • Bit 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bits 3:0 – SCDL3:0: Short-circuit Detection Level These bits set the RSENSE voltage level for detection of Short-circuit in the discharge direction, ...
Page 131
... BPDUV – Battery Protection Deep Under Voltage Register Bit (0xF3) Read/Write Initial Value • Bit 7:6 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bits 5:4 – DUVT1:0: Deep Under-voltage Timing These bits set the Deep Under-voltage Protection delay. Table 22-7. DUVT1:0 00 ...
Page 132
... I-bit in the Status Register (SREG) are set, the MCU will jump to the Battery Protection interrupt vector. The application software must read the Battery Protection Interrupt Register to determine the cause of the interrupt. The interrupt flags will not be cleared when the interrupt routine is executed, they must be cleared by writing a logical one to them. ATmega406 132 7 6 ...
Page 133
... For this purpose, ATmega406 provides a Precharge FET (PC-FET) control output. This output is default enabled. If ATmega406 has entered the Power-off mode, all FET control outputs will be disabled. When a charger is connected, the CPU will wake up. When waking up from Power-off mode, the C-FET and D-FET control outputs will remain disabled while PC-FET is default enabled ...
Page 134
... FCSR – FET Control and Status Register Bit (0xF0) Read/Write Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATmega406, and will always read as zero. • Bit 5 – PWMOC: Pulse Width Modulation of OC output ATmega406 134 Rpc Rdf ...
Page 135
... Precharge FET will be enabled. When the PFD bit is cleared, the Precharge FET will be enabled. When the PFD bit is set (one), the Precharge FET will be disabled. This bit will be cleared when the CURRENT_PROTECTION is set (one) 2548E–AVR–07/06 ATmega406 135 ...
Page 136
... Cell Balancing ATmega406 incorporates cell balancing FETs. The chip provides one cell balancing FET for each battery cell in series. The FETs are directly controlled by the application software, allowing the cell balancing algorithms to be implemented in software. The FETs are connected in parallel with the individual battery cells. The cell balancing is illustrated in a four-cell configuration ...
Page 137
... Initial Value • Bit 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 3 – CBE4: Cell Balancing Enable 4 When this bit is set, the integrated Cell Balancing FET between terminals PV4 and PV3 will be enabled ...
Page 138
... TWI protocol. The PRTWI bit in enable TWI module. Figure 25-1. TWI Bus Interconnection SDA SCL ATmega406 138 ”PRR0 – Power Reduction Register 0” on page 36 Device 1 Device 2 Device 3 must be written to zero to ...
Page 139
... The device placing data on the bus. The device reading data from the bus. Figure 25-1, both bus lines are connected to the positive supply voltage through ”2-wire Serial Interface Characteristics” on page SDA SCL Data Stable Data Change ATmega406 229. Data Stable 139 ...
Page 140
... The following data packets will then be received by all the slaves that acknowledged the general call. Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. ATmega406 140 START STOP START ...
Page 141
... Addr MSB SDA SCL 1 START Data MSB SDA Master 1 2 SLA+R/W shows a typical data transmission. Note that several data bytes can be transmitted ATmega406 Addr LSB R Data LSB ACK Data Byte ACK 9 STOP, REPEATED ...
Page 142
... Note that all masters listen to the SCL line, effectively starting to count their SCL high and low Time-out periods when the combined SCL line goes high or low, respectively. ATmega406 142 Addr MSB ...
Page 143
... A STOP condition and a data bit. • A REPEATED START and a STOP condition. 2548E–AVR–07/06 TA low Line TB Masters Start Counting Low Period START SDA from Master A SDA from Master B SDA Line ATmega406 TA high TB low high Masters Start Counting High Period Master A Loses Arbitration, SDA A SDA 143 ...
Page 144
... SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. ATmega406 144 SCL SDA ...
Page 145
... TWI in Master mode, sending Start + SLA + R slave (a slave does not need to be connected to the bus for the condition to happen). 2. The TWI clock is 4 MHz, see “Calibrated Fast RC Oscillator” on page 26. ATmega406 TWI Clock frequency = ---------------------------------------------------------- - TWPS ⋅ ...
Page 146
... After the TWI has been addressed by own slave address or general call. • After the TWI has received a data byte. • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition. ATmega406 146 2548E–AVR–07/06 ...
Page 147
... TWBR7 TWBR6 TWBR5 TWBR4 R/W R/W R/W R for calculating bit rates TWINT TWEA TWSTA TWSTO R/W R/W R/W R ATmega406 TWBR3 TWBR2 TWBR1 TWBR0 R/W R/W R/W R ”Bit Rate Generator TWWC TWEN – TWIE R R ...
Page 148
... This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bits 1:0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. ATmega406 148 ...
Page 149
... Rate Generator Unit” on page TWD7 TWD6 TWD5 R/W R/W R TWA6 TWA5 TWA4 R/W R/W R ATmega406 Prescaler Value 145. The value of TWPS1:0 is used TWD4 TWD3 TWD2 TWD1 R/W R/W R/W R TWA3 TWA2 ...
Page 150
... Figure 25-10. TWI Address Match Logic, Block Diagram • Bit 0 – Res: Reserved Bit This bit is an unused bit in the ATmega406, and will always read as zero. 25.7 Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition ...
Page 151
... SLA TWINT set. Status code indicates SLA+W sent, ACK received ATmega406 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one Data A STOP 6 ...
Page 152
... START brne ERROR ATmega406 152 (1) C example TWCR = (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) while (!(TWCR & (1<<TWINT))) ; if ((TWSR & 0xF8) != START) ERROR(); Comments Send START condition Wait for TWINT flag set. This ...
Page 153
... MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); 7. ATmega406 Comments Load SLA_W into TWDR Register. Clear TWINT bit in TWCR to start transmission of address Wait for TWINT flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has been received ...
Page 154
... MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 25-12. Data Transfer in Master Transmitter Mode SDA SCL ATmega406 154 START condition REPEATED START condition Read bit (high level at SDA) Write bit (low level at SDA) ...
Page 155
... TWSTO Table 25-3. TWINT TWEA TWSTA TWSTO TWINT TWEA TWSTA TWSTO TWINT TWEA TWSTA TWSTO ATmega406 TWWC TWEN – Table 25-3). In order to enter MT mode, TWWC TWEN – TWWC TWEN – TWWC TWEN – ...
Page 156
... Data byte has been transmit- ted; ACK has been received 0x30 Data byte has been transmit- ted; NOT ACK has been received 0x38 Arbitration lost in SLA+W or data bytes ATmega406 156 Application Software Response To TWCR STA STO TWINT To/from TWDR Load SLA+W X ...
Page 157
... MT S SLA W A $08 $ $38 A $68 DATA From master to slave From slave to master 25-14). In order to enter a Master mode, a START condition must be transmitted. The for- ATmega406 DATA A P $28 R SLA S $ $30 Other master Other master continues continues ...
Page 158
... A REPEATED START condition is generated by writing the following value to TWCR: TWCR Value After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again new slave without transmitting a STOP condition. Repeated START ATmega406 158 Device 1 Device 2 Device 3 ...
Page 159
... Read data byte Read data byte ATmega406 TWEA Next Action Taken by TWI Hardware X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to Master Transmitter mode ...
Page 160
... Figure 25-16). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 25-16. Data Transfer in Slave Receiver Mode SDA SCL To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: ATmega406 160 MR S SLA R A ...
Page 161
... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes. 2548E–AVR–07/06 TWA6 TWA5 TWA4 TWA3 Device’s Own Slave Address TWINT TWEA TWSTA TWSTO ATmega406 TWA2 TWA1 TWA0 TWGCE TWWC TWEN – TWIE Table 25-5. 161 ...
Page 162
... Previously addressed with general call; data has been received; NOT ACK has been returned 0xA0 A STOP condition or repeated START condition has been received while still addressed as slave ATmega406 162 Application Software Response To TWCR STA STO TWINT To/from TWDR No TWDR action or X ...
Page 163
... Arbitration lost as master and addressed as slave by general call 2548E–AVR–07/06 S SLA W A $60 A $68 General Call A $70 A $78 DATA From master to slave From slave to master n ATmega406 DATA A DATA $80 $ $88 DATA A DATA $90 $ ...
Page 164
... Thus the master receiver receives all “1” as serial data. State 0xC8 is entered if the master demands additional data bytes (by transmitting ACK), even though the slave has transmitted the last byte (TWEA zero and expect- ing NACK from the master). ATmega406 164 Device 1 Device 2 ...
Page 165
... No TWDR action TWDR action ATmega406 TWEA Next Action Taken by TWI Hardware 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should ...
Page 166
... TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. ATmega406 166 S ...
Page 167
... Master Transmitter SLA+W A ADDRESS S = START Transmitted from master to slave ATmega406 TWEA Next Action Taken by TWI Hardware Wait or proceed current transfer 1 X Only the internal hardware is affected, no STOP condi- tion is sent on the bus. In all cases, the bus is released and TWSTO is cleared. ...
Page 168
... READ/WRITE bit. If they are not being addressed, they will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. This is summarized in Figure 25-22. Possible Status Codes Caused by Arbitration START ATmega406 168 Device 1 Device 2 Device 3 MASTER ...
Page 169
... Bus Connect/Disconnect logic, where SDA and SCL are the TWI SCL SDA TWBCIP TWBCIF TWBCIE – – R/W R ATmega406 DELAY ELEMENT START OUTPUT DELAY SET TWBCIF TWBCSR 8-BIT DATA BUS – TWBDT1 TWBDT0 TWBCIP R R/W R/W R/W ...
Page 170
... Connect/Disconnect occurs, i.e., when the TWBCIE bit is set. • Bit 5:3 - Res: Reserved Bits These bits are reserved bits in the ATmega406 and will always read as zero. • Bit 2:1 - TWBDT1, TWBDT0: TWI Bus Disconnect Time-out Period The TWBDT bits decides how long both the TWI data (SDA) and clock (SCL) signals must be low before generating the TWI Bus Disconnect Interrupt ...
Page 171
... TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register. 2548E–AVR–07/06 shows a block diagram of the JTAG interface and the On-chip Debug system. The ATmega406 ® ”Programming via the JTAG Interface” on page 171 ...
Page 172
... The debugger can also pull the RESET pin low to reset the whole system, assuming only open collectors on the reset line are used in the application. Figure 26-1. Block Diagram TDI TDO TCK TMS ATmega406 172 JTAG PROGRAMMING TAP INTERFACE CONTROLLER FLASH INSTRUCTION ...
Page 173
... TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. 2548E–AVR–07/06 1 Test-Logic-Reset Run-Test/Idle Select-DR Scan 1 0 ATmega406 1 Select-IR Scan Capture-DR Capture- Shift-DR 0 Shift-IR ...
Page 174
... A list of the On-chip Debug specific JTAG instructions is given in Instructions” on page ATmega406 174 Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for five TCK clock periods. ...
Page 175
... Private JTAG instruction for accessing On-chip debug system. 26.6.4 PRIVATE3; 0xB Private JTAG instruction for accessing On-chip debug system. 2548E–AVR–07/06 ® supports source level execution of Assembly programs assembled with Atmel Cor- ® ® Windows ATmega406 95/98/2000 and Microsoft Windows NT ® . 175 ...
Page 176
... JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system. ATmega406 176 7 ...
Page 177
... The details on programming through the JTAG interface and programming specific JTAG instructions are given in the section 2548E–AVR–07/06 ”Programming via the JTAG Interface” on page ATmega406 211. 177 ...
Page 178
... BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see ATmega406 178 (1) Size 1 ...
Page 179
... Figure 27-2 on page 181. The main difference between the two sections is: See Section “27.5.1” on page 183. Read-While-Write Features Which Section Can be Read During Programming? RWW Section NRWW Section ATmega406 for details on how to clear RWWSB. CPU Halted? NRWW Section No None Yes Table 27- ...
Page 180
... Figure 27-1. Read-While-Write vs. No Read-While-Write ATmega406 180 Read-While-Write (RWW) Section Z-pointer Addresses RWW No Read-While-Write (NRWW) Section Section Code Located in NRWW Section Can be Read During the Operation Z-pointer Addresses NRWW Section CPU is Halted During the Operation 2548E–AVR–07/06 ...
Page 181
... Start Boot Loader Boot Loader Flash Section Flashend 1. The parameters in the figure above are given in and Table 27-3 for further details. The Boot Lock bits can be set in software and ATmega406 Program Memory BOOTSZ = '10' 0x0000 Application Flash Section End RWW Start NRWW Application Flash Section ...
Page 182
... BLB0 Mode Note: Table 27-3. BLB1 Mode Note: ATmega406 182 Boot Lock Bit0 Protection Modes (Application Section) BLB02 BLB01 Protection No restrictions for SPM or LPM accessing the Application 1 1 section SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM ...
Page 183
... Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset (see 1. “1” means unprogrammed, “0” means programmed SPMIE RWWSB SIGRD RWWSRE R ATmega406 Table 27-7 on page 193 BLBSET PGWRT PGERS R/W R/W R/W R SPMEN ...
Page 184
... SPMEN bit remains high until the operation is completed. Writing any other combination than “100001”, “010001”, “001001”, “000101”, “000011” or “000001” in the lower five bits will have no effect. ATmega406 184 ”Reading the Fuse and Lock Bits from Software” on page 188 for 2548E– ...
Page 185
... Figure 27-3. Note that the Page Erase and Page Write operations are BIT 15 ZPCMSB PCMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE 1. The different variables used in Figure 27-3 ATmega406 Z12 Z11 Z10 ” ...
Page 186
... Page Write operation or by writing the RWWSRE bit in SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. ATmega406 186 ”Simple Assembly Code Example for a Boot Loader” on page 191 for an assembly 2548E– ...
Page 187
... Assembly Code Example for a Boot Loader” on for an example BLB12 BLB11 and Table 27-3 for how the different settings of the Boot Loader bits affect the ATmega406 ”Interrupts” on page BLB02 BLB01 1 bits). For future compatibility it ck 51. ...
Page 188
... Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Bit Rd Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. ATmega406 188 – – ...
Page 189
... Table 27-5 and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction Signature Row Addressing (1) (2) (3) (7) (5) (6) (4) (8) (9) (9) (9) (9) (10) (12) ATmega406 Z-Pointer Address 0x00 0x02 0x04 0x01 0x03 0x05 0x06 0x07 0x0C 0x0D 0x08 0x0A 0x0B 0x09 0x0E 0x0F ...
Page 190
... Table 27-5. Signature Byte V-ADC Cell2 Offse V-ADC Cell3 Offse V-ADC Cell4 Offset VPTAT CAL L VPTAT CAL H Notes: All other addresses are reserved for future use. ATmega406 190 Signature Row Addressing (12) t (12) t (12) (11) 1. Default FOSCCAL value after reset. 2. Slow RC oscillator Frequency in kHz 3. Slow RC Oscillator fastest timeout in µ ...
Page 191
... PAGESIZEB<=256 r0, Y+ r1, Y+ spmcrval, (1<<SPMEN) ;use subi for PAGESIZEB<=256 ;restore pointer ;not required for PAGESIZEB<=256 spmcrval, (1<<PGWRT) | (1<<SPMEN) ATmega406 Table 27-6 shows the typical program- Max Programming Time 3.7 ms 4.5 ms 191 ...
Page 192
... EEPROM write access is present Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence out spm ; restore SREG (to enable interrupts if originally enabled) out ret ATmega406 192 spmcrval, (1<<RWWSRE) | (1<<SPMEN) looplo, low(PAGESIZEB) ;init loop variable loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ;restore pointer r0, Z+ r1, Y+ Error ...
Page 193
... ATmega406 Boot Loader Parameters In Table 27-7 ming are given Table 27-7. Note: Table 27-8. Section Read-While-Write section (RWW) No Read-While-Write section (NRWW) Note: Table 27-9. Variable PCMSB PAGEMSB ZPCMSB ZPAGEMSB PCPAGE PCWORD 2548E–AVR–07/06 through Table 27-9, the parameters used in the description of the Self-Program- (1) Boot Size Configuration ...
Page 194
... Note: ATmega406 194 1. Z0: should be zero for all SPM commands, byte select for the LPM instruction. See ”Addressing the Flash During Self-Programming” on page 185 Z-pointer during Self-Programming. for details about the use of 2548E–AVR–07/06 ...
Page 195
... Memory Programming 28.1 Program And Data Memory Lock Bits The ATmega406 provides six Lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain the additional features listed in erased to “1” with the Chip Erase command. Table 28-1. Lock Bit Byte ...
Page 196
... Notes: 28.2 Fuse Bits The ATmega406 has two Fuse bytes. all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logi- cal zero, “0”, if they are programmed. 28.2.1 High Byte Table 28-3. Fuse High Byte – ...
Page 197
... The default value of BOOTSZ1:0 results in maximum Boot Size. See for details. 3. See ”WDTCSR – Watchdog Timer Control Register” on page 47 4. When unpgrogrammed, Internal RC Oscillator is used. Programming this fuse is for test pur- pose only, and should not be used in application. ATmega406 Default Value 1 (unprogrammed) 1 (unprogrammed, EEPROM not preserved) Table 27-7 on ...
Page 198
... ATmega406 device when 0x001 is 0x95). 28.4 Calibration Bytes The ATmega406 has calibration bytes for the Fast RC Oscillator, Slow RC Oscillator, internal voltage reference, internal temperature reference and each differential cell voltage input. These bytes reside in the high bytes in the signature address space. During Reset, the calibration byte for the Fast RC Oscillator is automatically written into the corresponding calibration register ...
Page 199
... Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 28.6.2 Signal Names In this section, some pins of the ATmega406 are referenced by signal names describing their functionality during parallel programming, see 200. Pins not described in the following table are referenced by pin names. ...
Page 200
... OE WR BS1 XA0 XA1 PAGEL DATA Table 28-8. Table 28-9. XA1 ATmega406 200 Pin Name Mapping Pin Name I/O Function Byte Select 2 (“0” selects low byte, “1” selects 2’nd high PA0 I byte). 0: Device is busy programming, 1: Device is ready for new PA1 O command ...