ATxmega128A4U Atmel Corporation, ATxmega128A4U Datasheet - Page 191

• Manufacturer Part Number: ATxmega128A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.5
15.5.1
8331A–AVR–07/11
Counter Operation
Changing the Period
Figure 15-2. Clock Selection
The Peripheral Clock (clk
in a device). A selection of the prescaler outputs from 1 to 1/2024 is directly available. In addition
the whole range from 1 to 2
The clock selection (CLKSEL) selects one of the clock prescaler outputs or an event channel for
the High Byte Counter (CNTH) and Low Byte Counter (CNTL). By using the Event System, any
event source such as an external clock signal on any I/O pin can be used as clock input.
By default no clock input is selected and the Counters are not running.
The Counters will always count in single slope mode. Each Counter counts down for each clock
cycle until it reaches BOTTOM, and then reloads the Counter with the Period Register value at
the following clok cycle.
Figure 15-3. Counter Operation
As shown in
access has higher priority than count, and reloads and will be immediate.
The Counter period is changed by writing a new TOP value to the Period Register. Since the
Counter is counting down, the Period Register can be written at any time without affecting the
current period as shown in
of odd waveforms.
CNT
clk
PER
CLKSEL
BOTTOM
Figure
MAX
TOP
Prescaler
Common
15-3, the counter can change the counter value while running. The write
{0,1,2,4,8,64,256,1024}
PER
Figure 15-4 on page
15
) is fed into the Common Prescaler (common for all Timer/Counters
time prescalings is available through the Event System.
clk
PER
/
clk
2
{0,...,15}
PER
/
CNT written
192. This prevents wraparound and generation
Event System
event channels
Atmel AVR XMEGA AU
CNT
events
"reload"
191