ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 108

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ATxmega64A3

Manufacturer Part Number
ATxmega64A3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64A3

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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9.4.5
9.4.6
8077H–AVR–12/09
Software reset
Program and Debug Interface Reset
Figure 9-6.
For information on configuration and use of the WDT, refer to the
Timer” on page
The Software reset makes it possible to issue a system reset from software by writing to the
Software Reset bit in the Reset Control Register.The reset will be issued within 1-2 system clock
CPU cycles after writing the bit. It is not possible to execute any instruction from a software reset
is requested and until it is issued.
Figure 9-7.
The Program and Debug Interface reset contains a separate reset source that is used to reset
the device during external programming and debugging. This reset source is only accessible
from debuggers and programmers.
SOFTWARE
CC
CC
Watchdog reset.
Software reset
117.
1-2 2MHz
1-2 2MHz Cycle
Cycles
Section 11. ”WDT – Watchdog
XMEGA A
108

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