RM9200 Atmel Corporation, RM9200 Datasheet - Page 59

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.7
2.7.1
ARM DDI 0029G
The program status registers
Condition code flags
31 30 29 28 27 26 25 24 23
N Z C V
The ARM7TDMI processor contains a CPSR and five SPSRs for exception handlers to
use. The program status registers:
•
•
•
The arrangement of bits is shown in Figure 2-6.
To maintain compatibility with future ARM processors, you must not alter any of the
reserved bits. One method of preserving these bits is to use a read-write-modify strategy
when changing the CPSR.
The remainder of this section describes:
•
•
•
The N, Z, C, and V bits are the condition code flags, you can set them by arithmetic and
logical operations. They can also be set by MSR and LDM instructions. The
ARM7TDMI processor tests these flags to determine whether to execute an instruction.
code flags
Condition
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode.
Condition code flags on page 2-13
Control bits on page 2-14
Reserved bits on page 2-15.
Note
Copyright © 1994-2001. All rights reserved.
•
Overflow
Carry or borrow or extend
Zero
Negative or less than
•
•
Reserved
•
•
Figure 2-6 Program status register format
8
•
7
I
6
F
5
T
Control bits
M4 M3 M2 M1 M0
4
3
Programmer’s Model
2
Mode bits
State bit
FIQ disable
IRQ disable
1
0
2-13