SAM3N4C Atmel Corporation, SAM3N4C Datasheet - Page 549

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SAM3N4C

Manufacturer Part Number
SAM3N4C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N4C

Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
30.7.6
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485
mode, the USART behaves as though in asynchronous or synchronous mode and configuration
of all the parameters is possible. The difference is that the RTS pin is driven high when the
transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical
connection of the USART to a RS485 bus is shown in
Figure 30-26. Typical Connection to a RS485 Bus
The USART is set in RS485 mode by programming the USART_MODE field in the Mode Regis-
ter (US_MR) to the value 0x1.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high
when a timeguard is programmed so that the line can remain driven after the last character com-
pletion.
when the timeguard is enabled.
Figure 30-27. Example of RTS Drive with Timeguard
Figure 30-27
Baud Rate
TXEMPTY
US_THR
TXRDY
Clock
Write
TXD
RTS
gives an example of the RTS waveform during a character transmission
USART
Start
Bit
D0
RXD
TXD
RTS
D1
D2
D3
D4
D5
D6
Figure
D7
Parity
Bit
30-26.
Stop
Bit
Differential
Bus
TG = 4
SAM3N
SAM3N
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549

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