SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 282

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Index
Bus cycles
Bus interface
Bus interface signals 3-3
Byte accesses 3-26, 3-27
C
Clock domains 5-10
Clocks 5-2
Code density 1-6
Condition code flags 2-13
Control bits 2-14
Coprocessor
Coprocessor connections
Coprocessor interface
Coprocessor register cycles 3-9
Coprocessors
Index-2
coprocessor register transfer 3-9
internal 3-7
merged I-S 3-8
nonsequential 3-5
sequential 3-6
use of nWAIT 3-29
cycle types 3-4
signals 3-3
busy-wait sequence 4-8
bidirectional bus 4-12
unidirectional bus 4-13
handshaking 4-6
about 4-2
absence of external 4-15
availability 4-3
connecting 4-12
connecting multiple 4-13
connecting single 4-12
consequences of busy-waiting 4-8
data operation sequence 4-10
data operations 4-10
external 4-15
interface
load and store operations 4-10
load sequence 4-11
privileged instructions 4-17
register transfer instructions 4-9
register transfer sequence 4-9
signaling 4-7
timing 7-14
signals 4-4
Copyright © 1994-2001. All rights reserved.
Core clocks B-22
Core scan chain arrangements B-4
CPA 4-7
CPB 4-7
CPnCPI 4-7
D
Data
Data Aborts B-32
Data bus control circuit 3-20
Data replication 3-28
Data timed signals 3-17
Data types 2-6
Data write bus cycle 3-20
Debug
undefined instructions 4-16
multiplexing 4-13
action of core 5-9
behavior of PC B-29
breakpoints B-29
bypass register B-14
clock switch during B-22
clock switch during test 5-11, B-23
clock switching 5-10
clocks 5-2
communications channel 5-16
communications channel registers
communications through the comms
control and status register format
control register B-48
control registers B-42
core clocks B-22
core state B-24
coupling breakpoints and
determining core state 5-12, B-24
determining system state 5-12, B-26
EmbeddedICE
entry into 5-6
hardware B-45
programming B-45
software B-46
5-16
channel 5-17
B-51
watchpoints B-52
block diagram B-41
timing B-54
entry into on breakpoint 5-7
entry into on debug request 5-8
entry into on watchpoint 5-8
exit B-26
exit sequence B-28
function and mapping of
host 5-4
ID code register B-14
instruction register B-8, B-15
interface 5-2
interface signals 5-6
interrupt driven use of comms
mask registers B-42
output enable and disable times due
priorities and exceptions B-32
programming restriction B-55
protocol converter 5-4
public instructions B-9
receiving a message from debugger
request B-30
reset period timing 7-24
return address calculation B-31
scan chain 0 B-18
scan chain 0 cells B-33
scan chain 1 B-19
scan chain 1 cells B-37
scan chain 2 B-19
scan chain 3 B-20
scan chains B-16
scan path select register B-15
sending a message to debugger 5-18
stages 5-2
EmbeddedICE registers B-40
channel 5-18
to HIGHZ TAP instruction 7-25
Data Aborts B-32
interrupts B-32
Prefetch Abort B-32
BYPASS B-12
CLAMP B-11
CLAMPZ B-11
EXTEST B-9
HIGHZ B-11
IDCODE B-12
INTEST B-12
RESTART B-10
SAMPLE/PRELOAD B-10
SCAN_N B-10
5-18
ARM DDI 0029G