SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 146

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Timings
6.2
6-4
Branch and branch with link
A branch instruction calculates the branch destination in the first cycle, while
performing a prefetch from the current PC. This prefetch is done in all cases because,
by the time the decision to take the branch has been reached, it is already too late to
prevent the prefetch.
During the second cycle a fetch is performed from the branch destination, and the return
address is stored in register 14 if the link bit is set.
The third cycle performs a fetch from the destination +L, refilling the instruction
pipeline. If the instruction is a branch with link (R14 is modified) four is subtracted from
R14 to simplify the return instruction from
subroutines to push R14 onto the stack and pop directly into PC upon completion.
The cycle timings are listed in Table 6-1 where:
•
•
•
Branch with link is not available in Thumb state.
pc is the address of the branch instruction
alu is the destination address calculated by the ARM7TDMI core
(alu) is the contents of that address.
Cycle
1
2
3
Note
Copyright © 1994-2001. All rights reserved.
Address
pc+2L
alu
alu+L
alu+2L
MAS[1:0]
i
i
i
Table 6-1 Branch instruction cycle operations
0
0
0
nRW
Data
(pc+2L)
(alu)
(alu+L)
nMREQ
0
0
0
SEQ
0
1
1
ARM DDI 0029G
. This allows
nOPC
0
0
0