SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 27

• Manufacturer Part Number: SAM3N00A
• Manufacturer: Atmel Corporation

7.5
7.6
11011AS–ATARM–04-Oct-10
Master to Slave Access
Peripheral DMA Controller
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in
Table 7-3.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4.
Instance name
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
0
1
2
3
USART0
USART0
UART0
UART0
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
TWI0
TWI0
ADC
DAC
SPI
SPI
SAM3N Master to Slave Access
Peripheral DMA Controller
Peripheral Bridge
Internal SRAM
Internal Flash
Internal ROM
Channel T/R
Masters
Slaves
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Receive
Receive
100 & 64 Pins
Cortex-M3 I/D Bus
x
x
x
x
x
x
x
x
x
x
Table
X
X
0
-
-
7-3.
48 Pins
SAM3N Summary
N/A
x
x
x
x
x
x
x
x
x
Cortex-M3 S Bus
X
X
1
-
-
PDC
X
X
X
2
-
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