AD7194 Analog Devices, AD7194 Datasheet - Page 32

• Manufacturer Part Number: AD7194
• Description: 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7194

• Resolution (bits): 24bit
• # Chan: 8
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7194
absolute input voltage range specifications when the analog
inputs are buffered and chop is disabled.
DIGITAL INTERFACE
As indicated in the On-Chip Registers section, the program-
mable functions of the AD7194 are controlled using a set of
on-chip registers. Data is written to these registers via the serial
interface of the part. Read access to the on-chip registers is also
provided by this interface.
All communication with the part must start with a write to the
communications register. After power-on or reset, the device
expects a write to its communications register. The data written
to this register determines whether the next operation is a read
operation or a write operation, and it determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the part begins with a
write operation to the communications register, followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register, followed by a read
operation from the selected register.
The serial interface of the AD7194 consists of four signals: CS ,
DIN, SCLK, and DOUT/ RDY . The DIN line is used to transfer
data into the on-chip registers and DOUT/ RDY is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN
or DOUT/ RDY ) occur with respect to the SCLK signal.
The DOUT/ RDY pin functions as a data ready signal also, the
line going low when a new data-word is available in the output
register. It is reset high when a read operation from the data
register is complete. It also goes high prior to the updating of
the data register to indicate when not to read from the device, to
ensure that a data read is not attempted while the register is
being updated. CS is used to select a device. It can be used to
decode the AD7194 in systems where several components are
connected to the serial bus.
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Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7194 using CS to decode the part.
timing for a read operation from the output shift register of the
AD7194, and
the input shift register. It is possible to read the same word from
the data register several times even though the DOUT/
returns high after the first read operation. However, care must
be taken to ensure that the read operations are completed
before the next output update occurs. In continuous read mode,
the data register can be read only once.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/ RDY lines are used to
communicate with the AD7194. The end of the conversion can
be monitored using the RDY bit or pin. This scheme is suitable
for interfacing to microcontrollers. If CS is required as a decoding
signal, it can be generated from a port pin. For microcontroller
interfaces, it is recommended that SCLK idle high between data
transfers.
The AD7194 can be operated with CS used as a frame synchro-
nization signal. This scheme is useful for DSP interfaces. In this
case, the first bit (MSB) is effectively clocked out by CS because
CS normally occurs after the falling edge of SCLK in DSPs. The
SCLK can continue to run between data transfers, provided the
timing numbers are obeyed.
The serial interface can be reset by writing a series of 1s to the
DIN input. If a Logic 1 is written to the AD7194 DIN line for
at least 40 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface is lost due to a software error or a glitch in the system.
Reset returns the interface to the state in which it expects a write
to the communications register. This operation resets the
contents of all registers to their power-on values. Following a
reset, the user should allow a period of 200 μs before addressing
the serial interface.
The AD7194 can be configured to continuously convert or to
perform a single conversion (see Figure 24 through Figure 26).
Figure 4
shows the timing for a write operation to
Figure 3
shows the
RDY line