AD9251 Analog Devices, AD9251 Datasheet - Page 2

• Manufacturer Part Number: AD9251
• Description: 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9251

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9251
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings .......................................................... 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 20
REVISION HISTORY
10/09—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Change to Table 1 ............................................................................. 4
Moved Timing Diagrams................................................................. 8
Deleted Table 11; Renumbered Sequentially .............................. 22
Changes to Internal Reference Connection Section .................. 23
Moved Channel/Chip Synchronization Section ......................... 26
Change to Table 15 ......................................................................... 30
Changes to Reading the Memory Map Register
Table Section ................................................................................... 31
Changes to Table 16 ........................................................................ 32
7/09—Revision 0: Initial Version
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
AD9251-80 .................................................................................. 13
AD9251-65 .................................................................................. 15
AD9251-40 .................................................................................. 16
AD9251-20 .................................................................................. 17
ADC Architecture ...................................................................... 20
Analog Input Considerations .................................................... 20
Rev. A | Page 2 of 36
Built-In Self-Test (BIST) and Output Test .................................. 28
Serial Port Interface (SPI) .............................................................. 29
Memory Map .................................................................................. 31
Applications Information .............................................................. 35
Outline Dimensions ....................................................................... 36
Voltage Reference ....................................................................... 23
Clock Input Considerations ...................................................... 24
Channel/Chip Synchronization ................................................ 26
Power Dissipation and Standby Mode .................................... 26
Digital Outputs ........................................................................... 27
Timing ......................................................................................... 27
Built-In Self-Test (BIST) ............................................................ 28
Output Test Modes ..................................................................... 28
Configuration Using the SPI ..................................................... 29
Hardware Interface ..................................................................... 30
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Reading the Memory Map Register Table ............................... 31
Open Locations .......................................................................... 31
Default Values ............................................................................. 31
Memory Map Register Table ..................................................... 32
Memory Map Register Descriptions ........................................ 34
Design Guidelines ...................................................................... 35
Ordering Guide .......................................................................... 36