AD9276 Analog Devices, AD9276 Datasheet - Page 8

• Manufacturer Part Number: AD9276
• Description: Octal LNA/VGA/AAF/12-Bit ADC and CW I/Q Demodulator
• Manufacturer: Analog Devices

Specifications of AD9276

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 80MSPS
• Interface: LVDS,Ser
• Analog Input Type: SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: n/a
• Pkg Type: QFP

AD9276
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
Table 3.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
LO GENERATION
1
2
3
4
5
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
Can be adjusted via the SPI.
Measurements were made using a part soldered to FR-4 material.
t
RESET edge to rising 4LO edge.
SAMPLE
Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data-to-Data Skew (t
Wake-Up Time (Standby), GAIN+ = 0.5 V
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Uncertainty (Jitter)
4LO Frequency
LO Divider RESET Setup Time
LO Divider RESET Hold Time
LO Divider RESET High Pulse Width
40 MSPS (Mode I)
65 MSPS (Mode II)
80 MSPS (Mode III)
/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
2
1
F
R
) (20% to 80%)
) (20% to 80%)
2, 3
FRAME
PD
DATA
DATA-MAX
)
)
)
EL
4
4
EH
FCO
CPD
)
)
)
5
− t
)
5
4
DATA-MIN
)
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
Full
Full
Full
Full
Rev. 0 | Page 8 of 48
Min
10
10
10
(t
(t
(t
(t
4
5
5
20
SAMPLE
SAMPLE
SAMPLE
SAMPLE
/2) + 1.5
/2) + 1.5
/24) − 300
/24) − 300
IN
Typ
t
2
1
6.25
6.25
(t
300
300
(t
(t
(t
±100
8
<1
= 5 MHz, full temperature, unless otherwise noted.
FCO
SAMPLE
SAMPLE
SAMPLE
SAMPLE
+ (t
/2) + 2.3
/2) + 2.3
/24)
/24)
SAMPLE
/24)
Max
40
65
80
(t
(t
(t
(t
±350
40
SAMPLE
SAMPLE
SAMPLE
SAMPLE
/2) + 3.1
/2) + 3.1
/24) + 300
/24) + 300
Unit
MHz
MHz
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
μs
ms
Clock
cycles
MHz
ns
ns
ns
MHz
ps rms