AD9219 Analog Devices, AD9219 Datasheet
AD9219
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AD9219 Summary of contents
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... The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI). The AD9219 is available in an RoHS compliant, 48-lead LFCSP specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1 ...
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... AD9219 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Diagrams .............................................................................. 8 Absolute Maximum Ratings .......................................................... 10 Thermal Impedance ................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Equivalent Circuits ......................................................................... 13 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 20 REVISION HISTORY 12/11— ...
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... Changes to Reading the Memory Map Table Section ................ 32 Changes to Output Signals Section ............................................... 36 Changes to Figure 71 ...................................................................... 36 Changes to Default Operation and Jumper Selection Settings Section ................................................ 37 Changes to Alternative Analog Input Drive Configuration Section .............................................................................................. 38 Changes to Figure 74 ...................................................................... 40 Changes to Table 17 ........................................................................ 48 Changes to Ordering Guide ........................................................... 52 4/06—Revision 0: Initial Version Rev Page AD9219 ...
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... Full 1.7 1.8 1.9 Full 130 142 Full 30 32 Full 295 313 Full 2 5.8 Full 72 Full −100 Full −100 Rev Page Data Sheet AD9219-65 Min Typ Max Unit 10 Bits Guaranteed ±1 ±8 mV ±2 ±8 mV ±2 ±3 ±0.3 ±0 ±0.15 ±0.4 LSB ±0.3 ±0.75 LSB ± ...
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... Full 71 82 Full 80 Full 79 Full −84 Full −82 −71 Full −80 Full −79 Full −90 Full −90 −77 Full −90 Full −88 25°C 81.5 25°C 79.5 Rev Page AD9219 AD9219-65 Min Typ Max Unit 60.2 dB 60.2 dB 59.0 60.2 dB 60.1 dB 60.1 dB 60.1 dB 58.8 60.0 dB 59.8 dB 9.71 Bits 9.71 Bits 9.51 9.71 Bits 9.69 Bits ...
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... Full 1.79 Full 0.05 LVDS Full 247 454 Full 1.125 1.375 Offset binary LVDS Full 150 250 Full 1.10 1.30 Offset binary Rev Page Data Sheet AD9219-65 Min Typ Max Unit CMOS/LVDS/LVPECL 250 mV p-p 1 kΩ 1.5 pF 1.2 3 kΩ 0.5 pF 1.2 3 kΩ ...
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... SAMPLE (t /20) − 300 (t /20) (t /20) + 300 SAMPLE SAMPLE SAMPLE (t /20) − 300 (t /20) (t /20) + 300 SAMPLE SAMPLE SAMPLE ±50 ±150 600 375 8 500 <1 2 AD9219 Unit MSPS MSPS μs CLK cycles ps ps rms CLK cycles ...
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... AD9219 TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – x ...
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... – – – – – – – 9 Figure 4. 10-Bit Stream, LSB First Rev Page AD9219 LSB – – – – – – 8 ...
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... AD9219 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − x AGND SDIO/ODM AGND PDWN, SCLK/DTP, CSB ...
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... ADC A Digital Output Complement ADC A Digital Output True Frame Clock Output Complement Frame Clock Output True Data Clock Output Complement Data Clock Output True Serial Clock/Digital Test Pattern Serial Data IO/Output Driver Mode Rev Page AD9219 AVDD 36 AVDD 35 VIN – VIN + A ...
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... AD9219 Pin No. Mnemonic 30 CSB 31 PDWN 33 VIN + A 34 VIN − VIN − VIN + B 40 RBIAS 41 SENSE 42 VREF 43 REFB 44 REFT 47 VIN + C 48 VIN − C Description Chip Select Bar Power-Down ADC A Analog Input True ADC A Analog Input Complement ADC B Analog Input Complement ...
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... Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V AND PDWN Rev Page DRVDD V V D– DRGND Figure 9. Equivalent Digital Output Circuit 1kΩ SCLK/DTP 30kΩ Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit 100Ω RBIAS Figure 11. Equivalent RBIAS Circuit AD9219 ...
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... AD9219 AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page Data Sheet 6kΩ ...
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... FREQUENCY (MHz) = 120 MHz AIN = –0.5dBFS SNR = 59.93dB ENOB = 9.66 BITS –20 SFDR = 63.51dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) = 170 MHz AD9219 MSPS SAMPLE MSPS SAMPLE MSPS SAMPLE ...
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... AD9219 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with f = 190 MHz –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 22. Single-Tone 32k FFT with f = 250 MHz p-p, SFDR ...
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... IMD2 = 79.56dBc –20 IMD3 = 79.66dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 32. Two-Tone 32k FFT with MHz and f IN1 MSPS SAMPLE AD9219 2V p-p, SNR – MSPS SAMPLE MHz, IN2 MHz, IN2 ...
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... AD9219 0 AIN1 AND AIN2 = –7dBFS –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 33. Two-Tone 32k FFT with MHz and f IN1 MSPS SAMPLE 0 AIN1 AND AIN2 = –7dBFS –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 34 ...
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... FREQUENCY (MHz) Figure 41. Noise Power Ratio (NPR MSPS SAMPLE 0 –1 –2 –3dB CUTOFF = 315MHz –3 –4 –5 –6 –7 –8 –9 – 100 150 200 250 300 350 FREQUENCY (MHz) SAMPLE AD9219 25 30 400 450 500 = 65 MSPS ...
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... Wideband A/D Converters” (Volume 39, April 2005) for more information at www.analog.com. In general, the precise values depend on the application. The analog inputs of the AD9219 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that V recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 44 to Figure 47 ...
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... SFDR (dBc SNR (dB 0.2 0.4 0.6 0.8 1.0 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 46. SNR/SFDR vs. Common-Mode Voltage 2.4 MHz MSPS IN SAMPLE SFDR (dBc SNR (dB 0.2 0.4 0.6 0.8 1.0 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 47. SNR/SFDR vs. Common-Mode Voltage MHz MSPS IN SAMPLE AD9219 1.4 1.6 1.4 1.6 ...
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... In the case of the AD9219, the largest input span available p-p. Differential Input Configurations There are several ways to drive the AD9219 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the ...
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... CLK– the AD9219. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode ...
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... Figure 57. Ideal SNR vs. Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 58 and Figure 59, the power dissipated by ) the AD9219 is proportional to its sample rate. The digital power A dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS × ...
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... Data Sheet By asserting the PDWN pin high, the AD9219 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the SPI features are changed before the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset ...
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... AD9219 EYE: ALL BITS 500 0 –500 –1ns –0.5ns 0ns 100 50 0 –100ps 0ps Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only EYE: ALL BITS 200 0 –200 –1ns – ...
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... Data Sheet Two output clocks are provided to assist in capturing data from the AD9219. The DCO is used to clock the output data and is equal to five times the sample clock (CLK) rate. Data is clocked out of the AD9219 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) Table 9 ...
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... Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9219 inverts the bit stream with relation to the ITU standard. Table 10. PN Sequence Initial ...
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... ADC to a nominal 232 MSPS. Therefore imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Voltage Reference A stable, accurate 0.5 V voltage reference is built into the AD9219. This is gained up internally by a factor of 2, setting V to 1.0 V, which results in a full-scale differential input span REF p-p. The V VREF pin can be driven externally with a 1 ...
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... The analog input full- scale range of the ADC equals twice the voltage of the reference pin for either an internal or an external reference configuration. If the reference of the AD9219 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. Figure 66 depicts how the internal reference voltage is affected by loading ...
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... If multiple SDIO pins share a common connection, care should be taken to ensure that proper V same load for each AD9219, Figure 68 shows the number of SDIO pins that can be connected together and the resulting V level. This interface is flexible enough to be controlled by either ...
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... AD9219 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 68. SDIO Pin Loading CSB SCLK DON’T CARE R A12 SDIO DON’ ...
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... Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES When the AD9219 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature. ...
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... Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset off 0 = off (default) (default) 8-bit Chip ID Bits [7:0] (AD9219 = 0x03), (default Clock Clock Data Data Channel Channel Channel Channel DCO FCO ...
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... Rev Page AD9219 Default (LSB) Value Default Notes/ Bit 1 Bit 0 (Hex) Comments 00 = offset binary 0x00 Configures the (default) outputs and the 01 = twos complement format of the data. ...
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... AD9219. An exposed continuous copper plane on the PCB should mate to the AD9219 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. ...
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... Figure 73 to Figure 77). Figure 71 shows the typical bench characterization setup used to evaluate the ac performance of the AD9219 critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter ...
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... AD9219 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9219 Rev. A evaluation board. POWER: Connect the switching power supply that is provided in the evaluation kit between a rated 100 240 V ac wall outlet and P503. ...
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... Remove R305, R306, R313, R314, R405, R406, R412, and R424 to configure the AD8332. In this configuration, L301 to L308 and L401 to L408 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev Page AD9219 ...
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... AD9219 VGA INPUT CONNECTION INH1 CHANNEL A R101 P101 DNP AIN R102 64.9Ω VGA INPUT CONNECTION CHANNEL B P103 AIN P106 DNP VGA INPUT CONNECTION INH3 AIN CHANNEL C R127 P105 DNP AIN R129 R128 0Ω 64.9Ω AVDD_DUT VGA INPUT CONNECTION INH4 CHANNEL D P107 ...
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... CHB B – AVDD CHC AVDD CHC C – VIN CHD – VIN CHD D – Rev Page AD9219 GND RSET S10 32 7 VREF ...
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... AD9219 POPULATE L301-L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. 10kΩ R313 10kΩ DNP C311 0.1µF C312 0.1µF R315 C315 10kΩ 10µF DNP: DO NOT POPULATE Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit ...
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... J401 PICVCC 1 2 PICVCC GP1 3 4 GP1 GP0 5 6 GP0 MCLR/GP3 7 8 MCLR/GP3 9 10 PIC PROGRAMMING HEADER GAIN NEGATIVE SLOPE GAIN POSITIVE PIN MODE 0.018µF 274Ω C420 R416 8 AVDD_5V AVDD_5V 2 1 GAIN LO GAIN HI PIN HILO OPTIONAL AD9219 ...
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... AD9219 Figure 77. Evaluation Board Schematic, Power Supply Inputs Rev Page Data Sheet 05726-019 GND GND 1 1 GND GND 1 1 ...
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... Data Sheet Figure 78. Evaluation Board Layout, Primary Side Rev Page AD9219 ...
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... AD9219 Figure 79. Evaluation Board Layout, Ground Plane Rev Page Data Sheet ...
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... Data Sheet Figure 80. Evaluation Board Layout, Power Plane Rev Page AD9219 ...
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... AD9219 Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page Data Sheet ...
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... Diode DO-214AA SMC Fuse 1210 6.0 V, 2.2 A trip- current resettable fuse Choke coil 2020 10 μ 190 Ω @ 100 MHz Rev Page AD9219 Manufacturer’s Manufacturer Part Number Murata GRM155R71C104KA88D Murata GRM1555C1H2R2GZ01B Murata GRM219R60J106KE19D Murata GRM188C70J225KE20D Murata GRM155R71H102KA01D ...
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... AD9219 Item Qty. Reference Designator 19 12 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 20 1 JP301 21 2 J205, J402 22 1 J201 to J204 23 1 J401 24 8 L501, L502, L503, L504, L505, L506, L507, L508 25 4 L309, L310, L409, L410 ...
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... ADT1-1WT, 1:1 impedance ratio transformer IC SOT-223 ADP3339AKC-1.8, 1.5 A, 1.8 V LDO regulator IC LFCSP, AD8332ACP, CP-32 ultralow noise precision dual VGA IC SOT-223 ADP3339AKC-5 Rev Page AD9219 Manufacturer’s Manufacturer Part Number NIC NRC04F4990TRF Components NRC04F1003TRF NIC Components NIC NRC04F4121TRF Components Susumu RR0510R-49R9-D NRC04F4991TRF NIC Components BC ...
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... Flash prog mem 1k × 14, RAM size 64 × MHz speed, PIC12F controller series Rev Page Data Sheet Manufacturer’s Manufacturer Part Number Analog Devices ADP3339AKCZ-3.3 Analog Devices AD9219BCPZ-65 Analog Devices ADR510ARTZ Analog Devices AD9515BCPZ Fairchild NC7WZ07P6X_NL Fairchild NC7WZ16P6X_NL Microchip PIC12F629-I/SN ...
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... Temperature 1 Model Notes Range AD9219ABCPZ-40 −40°C to +85°C AD9219ABCPZRL7-40 −40°C to +85°C AD9219ABCPZ-65 −40°C to +85°C AD9219ABCPZRL7-65 −40°C to +85°C 2 AD9219-65EBZ RoHS Compliant Part. 2 Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board. 7.10 0.60 MAX 7.00 SQ 6.90 0.60 MAX 0.50 6.85 REF 6. ...
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... AD9219 NOTES Rev Page Data Sheet ...
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... Data Sheet NOTES Rev Page AD9219 ...
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... AD9219 NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05726-0-12/11(E) Rev Page Data Sheet ...