AD7323 Analog Devices, AD7323 Datasheet - Page 7

• Manufacturer Part Number: AD7323
• Description: 500 kSPS, 4-Channel, Software Selectable True bipolar Input, 12-Bit Plus Sign A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7323

• Resolution (bits): 13bit
• # Chan: 4
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

TIMING SPECIFICATIONS
V
internal/external, T
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
10
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t
2
DD
= 12 V to 16.5 V, V
V
50
10
16 × t
75
12
25
45
26
57
0.4 × t
0.4 × t
13
40
10
4
2
750
500
25
CC
DOUT
SCLK
DIN
< 4.75 V
CS
A
SCLK
THREE-
SCLK
SCLK
STATE
= T
SS
Limit at T
MAX
= −12 V to −16.5 V, V
WRITE
ZERO
t
2
to T
1
V
50
10
16 × t
60
5
20
35
14
43
0.4 × t
0.4 × t
8
22
9
4
2
750
500
25
2 IDENTIFICATION BITS
t
ADD1
CC
3
MIN
t
SEL1
= 4.75 V to 5.25 V
9
REG
MIN
. Timing specifications apply with a 32 pF load, unless otherwise noted.
SCLK
SCLK
SCLK
2
, T
ADD0
MAX
SEL2
REG
3
SIGN
CC
MSB
= 2.7 V to 5.25 V, V
4
Figure 2. Serial Interface Timing Diagram
DB11
t
t
6
4
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
μs typ
t
CONVERT
t
10
5
t
DB10
7
Rev. A | Page 7 of 36
Description
t
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power-up from autostandby
Power-up from full shutdown/autoshutdown mode, internal reference
Power-up from full shutdown/autoshutdown mode, external reference
SCLK
DRIVE
13
2
= 1/f
at 20 ns, the mark space ratio must be limited to 50:50.
DB2
= 2.7 V to 5.25 V, V
SCLK
14
t
5
DB1
LSB
15
DB0
DON’T
CARE
16
DRIVE
THREE-STATE
t
8
≤ V
DRIVE
CC
t
QUIET
, V
) and timed from a voltage level of 1.6 V.
1
t
REF
1
= 2.5 V to 3.0 V
AD7323