AD7265 Analog Devices, AD7265 Datasheet

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AD7265

Manufacturer Part Number
AD7265
Description
Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD7265

Resolution (bits)
12bit
# Chan
12
Sample Rate
1MSPS
Interface
Ser,SPI
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
Uni (Vref),Uni (Vref) x 2
Adc Architecture
SAR
Pkg Type
CSP,QFP

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FEATURES
Dual 12-bit, 3-channel ADC
Throughput rate: 1 MSPS
Specified for V
Power consumption
Pin-configurable analog inputs
70 dB SINAD at 50 kHz input frequency
Accurate on-chip reference: 2.5 V
Dual conversion with read 875 ns, 16 MHz SCLK
High speed serial interface
−40°C to +125°C operation
Shutdown mode: 1 μA maximum
32-lead LFCSP and 32-lead TQFP
2 MSPS version,
GENERAL DESCRIPTION
The AD7265
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates of up to 1 MSPS. The
device contains two ADCs, each preceded by a 3-channel
multiplexer, and a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 30 MHz.
The conversion process and data acquisition use standard
control inputs allowing easy interfacing to microprocessors or
DSPs. The input signal is sampled on the falling edge of CS ;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. The AD7265 uses advanced
design techniques to achieve very low power dissipation at high
throughput rates. With 5 V supplies and a 1 MSPS throughput rate,
the part consumes 4 mA maximum. The part also offers flexible
power/throughput rate management when operating in normal
mode, because the quiescent current consumption is so low.
The analog input range for the part can be selected to be a 0 V
to V
complement output coding. The AD7265 has an on-chip 2.5 V
reference that can be overdriven when an external reference is
preferred. This external reference range is 100 mV to V
AD7265 is available in 32-lead LFCSP and 32-lead TQFP.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
7 mW at 1 MSPS with 3 V supplies
17 mW at 1 MSPS with 5 V supplies
12-channel single-ended inputs
6-channel fully differential inputs
6-channel pseudo differential inputs
±0.2% maximum @ 25°C, 20 ppm/°C maximum
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
REF
(or 2 × V
1
is a dual, 12-bit, high speed, low power, successive
DD
REF
AD7266
of 2.7 V to 5.25 V
) range, with either straight binary or twos
DD
. The
Differential/Single-Ended Input, Dual
1 MSPS, 12-Bit, 3-Channel SAR ADC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
PRODUCT HIGHLIGHTS
1. Two Complete ADC Functions Allow Simultaneous
2. High Throughput with Low Power Consumption.
3. The AD7265 offers both a standard 0 V to V
4. No Pipeline Delay.
1
V
V
V
V
V
V
V
V
V
V
V
V
Protected by U.S. Patent No. 6,681,332.
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
Sampling and Conversion of Two Channels.
Each ADC has three fully/pseudo differential pairs, or six
single-ended channels, as programmed. The conversion
result of both channels is simultaneously available on
separate data lines, or in succession on one data line if only
one serial port is available.
The AD7265 offers a 1 MSPS throughput rate with 9 mW
maximum power dissipation when operating at 3 V.
and a 2 × V
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a
input and once off conversion control.
AGND AGND AGND D
REF SELECT
MUX
MUX
REF
FUNCTIONAL BLOCK DIAGRAM
REF
BUF
BUF
T/H
T/H
input range.
CAP
©2006 Analog Devices, Inc. All rights reserved.
APPROXIMATION
APPROXIMATION
SUCCESSIVE
SUCCESSIVE
B
D
CONTROL
CAP
12-BIT
LOGIC
12-BIT
Figure 1.
ADC
ADC
A
DGND
AV
DD
AD7265
DRIVERS
DRIVERS
OUTPUT
OUTPUT
DGND
DV
DD
AD7265
www.analog.com
REF
input range
D
SCLK
CS
RANGE
SGL/DIFF
A0
A1
A2
V
D
DRIVE
OUT
OUT
A
B
CS

Related parts for AD7265

AD7265 Summary of contents

Page 1

... High Throughput with Low Power Consumption. The AD7265 offers a 1 MSPS throughput rate with 9 mW maximum power dissipation when operating The AD7265 offers both a standard and a 2 × ...

Page 2

... Rev. A Changes to Format .............................................................Universal Changes to Reference Input/Output Section ................................ 4 Changes to Table 4............................................................................ 7 Changes to Terminology Section.................................................. 11 Changes to Figure 24 and Differential Mode Section................ 15 Changes to Figure 29...................................................................... 16 Changes to AD7265 to ADSP-BF53x Section............................. 24 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 Digital Inputs .............................................................................. 18 V ............................................................................................ 18 DRIVE Modes of Operation ....................................................................... 19 Normal Mode ...

Page 3

... IN− CM REF V ± IN− CM REF Rev Page AD7265 Test Conditions/Comments kHz sine wave; differential mode kHz sine wave; single-ended and IN pseudo differential modes kHz sine wave; differential mode kHz sine wave; single-ended and ...

Page 4

... AD7265 Parameter DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT 8 Reference Output Voltage Long-Term Stability 2 Output Voltage Hysteresis Reference Input Voltage Range DC Leakage Current Input Capacitance Output Impedance CAP CAP Reference Temperature Coefficient V Noise REF LOGIC INPUTS Input High Voltage, V INH ...

Page 5

... A > 85°C to 125° and D B are three-state disabled OUT OUT = high impedance OUT OUT high impedance OUT OUT high impedance OUT OUT ) and timed from a voltage level of 1 AD7265 1 . ...

Page 6

... AD7265 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter V to AGND DGND DGND DRIVE V to AGND DRIVE AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND V to AGND REF Input Current to Any Pin Except 1 Supplies ...

Page 7

... ADC A and ADC B. In addition, Pin D decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7265 through the Analog Supply Voltage, 2 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The DD AV and transient basis ...

Page 8

... This pin should be decoupled to DGND. The voltage at this pin may be different than that at AV should never exceed either by more than 0 Digital Supply Voltage, 2 5.25 V. This is the supply voltage for all digital circuitry on the AD7265. The DV DD and AV voltages should ideally be at the same potential and must not be more than 0.3 V apart even transient basis ...

Page 9

... CODE Figure 8. Typical DNL 1 5V DIFFERENTIAL MODE 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 3000 CODE Figure 9. Typical INL AD7265 = 3V DRIVE = 1MSPS 400 450 500 = 3V DRIVE 3500 4000 = 3V DRIVE 3500 4000 ...

Page 10

... AD7265 1.0 V DIFFERENTIAL MODE 0.8 POSITIVE DNL 0.6 0.4 POSITIVE INL 0.2 0 –0.2 NEGATIVE INL –0.4 –0.6 NEGATIVE DNL –0.8 –1.0 0 0.5 1.0 1.5 V (V) REF Figure 10. Linearity Error vs. V 12.0 11.5 11 10.5 SINGLE-ENDED MODE 10 9.5 DD SINGLE-ENDED MODE 9 8.5 DIFFERENTIAL MODE DIFFERENTIAL MODE 8.0 7.5 7.0 0 0.5 1.0 1.5 2.0 2.5 3.0 V (V) REF Figure 11. Effective Number of Bits vs. V 2.5010 2 ...

Page 11

... N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Therefore, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7265 defined as THD where the rms amplitude of the fundamental. 1 ...

Page 12

... AD7265 The AD7265 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. ...

Page 13

... CIRCUIT INFORMATION The AD7265 is a fast, micropower, dual, 12-bit, single-supply, ADC that operates from a 2 5.25 V supply. When operated from either supply, the AD7265 is capable of throughput rates of 1 MSPS when provided with a 16 MHz clock. The AD7265 contains two on-chip, differential track-and-hold amplifiers, two successive approximation ADCs, and a serial interface with two separate data output pins ...

Page 14

... Analog Input Selection section. SOURCE Single-Ended Mode The AD7265 can have a total of 12 single-ended analog input channels. In applications where the signal source has high impedance recommended to buffer the analog input before R = 0Ω applying it to the ADC. The analog input range can be pro- ...

Page 15

... V range, respectively. The common mode REF REF must be in this range to guarantee the functionality of the AD7265. When a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude −V +V corresponding to the digital codes 4096. If the REF 2 × ...

Page 16

... AD7265 Using an Op Amp Pair An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7265. The circuit configurations illustrated in Figure 26 and Figure 27 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively ...

Page 17

... If the mode is changed from fully differential to pseudo-differential, for example, then the acquisition time would start again from this point. The selected input channels are decoded as shown in The analog input range of the AD7265 can be selected × V REF ...

Page 18

... V ± V Input Range REF REF DIGITAL INPUTS The digital inputs applied to the AD7265 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs can be applied and are not restricted by range is used. In the V REF /4096 when the ...

Page 19

... MODES OF OPERATION The mode of operation of the AD7265 is selected by controlling the (logic) state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial power- down mode, and full power-down mode. After a conversion pulled high determines which initiated, the point at which power-down mode, if any, the device enters ...

Page 20

... AD7265 To exit this mode of operation and power up the AD7265 again, a dummy conversion is performed. On the falling edge the device begins to power up and continues to power up as long held low until after the falling edge of the 10 SCLK. The device is fully powered up after approximately 1 μs has elapsed, and valid data results from the next conversion, as shown in Figure 36 ...

Page 21

... AD7265 must be in partial power-down for at least 67 μs in order for this power-up time to apply. When power supplies are first applied to the AD7265, the ADC may power up in either of the power-down modes or normal mode. Because of this best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion ...

Page 22

... SCLK can be ignored for the purposes of the timing descriptions in B. This OUT this section falling edge of SCLK is coincident with the A is shown. In OUT falling edge of acknowledged by the AD7265, and the next falling edge of SCLK will be the first registered after the falling edge ...

Page 23

... MICROPROCESSOR INTERFACING The serial interface on the AD7265 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7265 with some of the more common microcontroller and DSP serial interface protocols. AD7265 TO ADSP-218x The ADSP-218x family of DSPs interface directly to the AD7265 without any glue logic required ...

Page 24

... DSPs means only one serial port is necessary to read from both D pins simultaneously. Figure 44 shows both D OUT the AD7265 connected to Serial Port 0 of the OUT ADSP-BF53x. The SPORT0 Receive Configuration 1 register and SPORT0 Receive Configuration 2 register should be set up as outlined in Table 9 and Table 10. ...

Page 25

... AD7265 TO DSP563xx The connection diagram in Figure 46 shows how the AD7265 can be connected to the ESSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. There are two on-board ESSIs, and each operates in synchronous mode (Bit SYN = 1 in CRB register) with internally generated word length frame sync for both TX and RX (Bit FSL1 = 0 and Bit FSL0 = 0 in CRB) ...

Page 26

... However, the analog ground plane should be allowed to run under the AD7265 to avoid noise coupling. The power supply lines to the AD7265 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. ...

Page 27

... This board is a complete unit allowing control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board (such as, EVAL-AD7265CB), the EVAL-CONTROL BRD2, and transformer must be ordered. See the relevant evaluation board technical note for more information ...

Page 28

... AD7265 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04674-0-11/06(A) T Rev Page ...

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