AD6650 Analog Devices, AD6650 Datasheet
AD6650
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AD6650 Summary of contents
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... Smart antenna systems Software radios In-building wireless telephony PRODUCT DESCRIPTION The AD6650 is a diversity intermediate frequency-to-baseband (IF-to-baseband) receiver for GSM/EDGE. This narrow-band receiver consists of an integrated DVGA, IF-to-baseband I/Q demodulators, low-pass filtering, and a dual wideband ADC. The chip can accommodate IF input from 70 MHz to 260 MHz. ...
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... Changes to Ordering Guide .......................................................... 44 3/06—Revision 0: Initial Version LO Synthesis................................................................................ 22 LDO.............................................................................................. 23 AGC Loop/Relinearization ....................................................... 23 Serial Output Data Port............................................................. 24 Application Information................................................................ 26 Required Settings and Start-up Sequence for DC Correction ....................................................................................................... 26 Clocking the AD6650 ................................................................ 26 Driving the Analog Inputs ........................................................ 27 External Reference ..................................................................... 27 Power Supplies ............................................................................ 27 Digital Outputs ........................................................................... 28 Grounding ................................................................................... 28 Layout Information.................................................................... 28 Chip Synchronization ................................................................ 29 Microport Control.......................................................................... 30 External Memory Map ...
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... V 25°C V 25°C V 25°C V 25°C V 25° Full IV 24 Full IV −15 Full Rev Page AD6650 Typ Max Unit 260 MHz 0.094 dB ±0.047 3.5 3.64 MHz 77 dB −79 dBc/Hz −87 dBc/Hz −103 dBc/Hz −112 dBc/Hz − ...
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... Temp DVDD Full AVDD Full 1 T AMBIENT 1 The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C to −40°C. Temp Test Level Min V V Full IV ...
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... Full IV DSCLK1 t Full IV DSCLKH t Full IV DSCLKL t Full IV DSCLKLL t Full IV DSDFS t Full IV DSDO0 t Full IV DSDO1 t Full IV DSDR Rev Page AD6650 Typ Max Unit 3.3 V CMOS VDD V 0 μA 7 μ 3.6 V p-p DVDD/2 V 7.5 kΩ 3.3 V CMOS/TTL VDD − 0.2 V 0.2 0.8 V 155 mA 360 mA 1.7 2.1 W ...
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... AD6650 MICROPROCESSOR PORT TIMING CHARACTERISTICS All timing specifications valid over VDD range of 3 3.45 V and VDDIO range of 3 3.45 V. Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation Parameter WRITE TIMING 1 WR (R/W) to RDY (DTACK) Hold Time Address/Data to WR (R/W) Setup Time Address/Data to RDY (DTACK) Hold Time ...
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... Figure 4. SCLK Switching Characteristics (Divide-by-2 or Even Integer) CLK t t DSCLKH DSCLKLL SCLK Figure 5. SCLK Switching Characteristics (Divide-by-3 or Odd Integer) SCLK t DSDR DR Figure 6. SCLK, DR Switching Characteristics SCLK t DSDFS SDFS Figure 7. SCLK, SDFS Switching Characteristics SCLK t t DSD0/ DSD1 Figure 8. SCLK, SDO0/SDO1 Switching Characteristics Rev Page AD6650 ...
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... AD6650 SYNC RD (DS) WR (R/W) CS A[2:0] D[7:0] RDY (DTACK) NOTES t 1. ACC FROM FALLING EDGE RISING EDGE OF RDY ACC RD (DS) WR (R/W) CS A[2:0] D[7:0] RDY (DTACK) NOTES t 1. ACC FROM FALLING EDGE RISING EDGE OF RDY ACC CLK Figure 9. SYNC Timing Inputs ...
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... ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED ACC FROM FALLING EDGE THE FALLING EDGE OF DTACK REQUIRES A MAXIMUM OF 13 CLK PERIODS. ACC Figure 13. MNM Microport Read Timing Requirements Rev Page HDS t HRW t DDTACK t HDS VALID ADDRESS HAM VALID DATA t DDTACK AD6650 ZD ...
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... AD6650 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage Input Voltage Output Voltage Swing Load Capacitance Junction Temperature Under Bias Storage Temperature Range Lead Temperature (5 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... AVDD AGND DNC AVDD AVDD AGND AGND AVDD AVDD AGND AGND AVDD AVDD AGND AGND AVDD REFGND REFT AGND AVDD VREF REFB AGND AD6650 11 AGND A BIN B BIN C AGND VLDO F CPOUT G AGND H AIN J AIN K AGND L 11 No. of Pins 13 19 ...
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... AD6650 Mnemonic Type DTACK (RDY) Output R/W (WR) Input MODE [2:0] Input JTAG TRST Input TCLK Input TMS Input TDO Output TDI Input ANALOG INPUTS AIN Input Input AIN BIN Input BIN Input PLL INPUTS CPOUT Output LF Input VLDO Output REFT Output REFB Output ...
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... IF FREQUENCY (MHz) Figure 17. Image vs. Frequency 0.2 0 –25°C –0.2 –0.4 –0.6 +25°C –0.8 –1.0 +85°C –1.2 –1 110 130 150 170 190 IF FREQUENCY (MHz) Figure 18. Gain Error vs. Frequency AD6650 –25°C +85°C 210 230 250 210 230 250 ...
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... SNR is the computed signal-to-noise ratio referred to full scale FS with a small input signal and the AD6650 in maximum gain. Input Second-Order Intercept (IIP2) A figure of merit used to determine a component’s or system’s susceptibility to intermodulation distortion (IMD) from its second-order nonlinearities. Two unmodulated carriers at a ...
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... EQUIVALENT CIRCUITS 1nH AIN/BIN 25Ω 75Ω CLAMP 1pF 2pF 75Ω 25Ω 1nH AIN/BIN Figure 19. Analog Input AVDD 20kΩ 20kΩ 5kΩ 2.5kΩ CLK 5pF 5kΩ 2.5kΩ CLK 20kΩ 20kΩ Figure 20. Clock Input Rev Page AD6650 1.3V ...
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... ADC and minimize signal clipping at the ADC input. The VGA has a maximum gain with a nominal step size of 0.094 dB. The amplifier serves as the input stage to the AD6650 and has a nominal input impedance of 200 Ω and a 4 dBm maximum input. I/Q Demodulators Frequency translation is accomplished with I/Q demodulators ...
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... It is essential to consider the dc offset of the signal at the point where the AGC of the AD6650 begins to range. This is important because once the signal or a blocker is in the range of the AGC loop, the dc signal that appears at the output of the AD6650 is modulated by the change in gain of the loop ...
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... Address 0x18 in the form the RCF is f RCF Decimation Phase Register The AD6650 uses the value stored in this register to preload the RCF counter. Therefore, instead of starting from 0, the counter is loaded with this value, thus creating a time offset in the output data. This data is stored in Address 0x19 as a 3-bit number. Time delays can be achieved in even units of the RCF input rate, which is typically ¼ ...
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... RCF Filter Length The maximum number of taps this filter can calculate, N given by Equation 10. The value N − written to the taps channel register within the AD6650 at Address 0x1B. ⎛ × ⎞ ⎜ ⎟ ≤ CLK RCF N min , 48 ⎜ ⎟ taps f ⎝ ...
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... The current estimate is held, so the last known dc content continues to be removed. The AI, AQ, BI, and BQ paths of the AD6650 are each treated independently in the dc correction circuitry because the analog paths are not guaranteed to match, and separate dc estimates need to be kept for each ...
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... AD6650. Each BIST register is independent, meaning that each channel can be tested independently at the same time. The BIST is a thorough test of the selected AD6650 digital signal path. With this test mode possible to use the internal pseudorandom generator to produce known test data. A signature register follows the fine dc correction block ...
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... AD6650 LO SYNTHESIS The AD6650 has a fully integrated quadrature LO synthesizer consisting of a voltage-controlled oscillator (VCO) and a phase- locked loop (PLL). Together these blocks generate quadrature IF LO signals for the demodulators. Figure 27 shows a block diagram of the LO synthesis block. Besides the usual PLL and VCO, there is also a programmable half-rate divider (Div-X and a fixed divide-by-4 quadrature divider that produces the final I and Q LO signals) ...
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... CP OUTPUT Figure 29. PFD Simplified Schematic and Timing (Locked) LDO The AD6650 includes an on-chip 2.6 V low dropout (LDO) voltage regulator that supplies the VCO and other sections of the PLL. A 0.22 μF bypass capacitor is required on the VLDO output to ensure stability. This LDO employs the same technology used in the anyCAP® ...
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... AD6650’s filters, this data is transferred into the serial data buffer. The internal serial controller initiates the SDFS on the next rising edge of the serial clock. In the AD6650, there are three modes in which the frame sync can be generated, which are described in the SDFS Modes section. ...
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... SDO pin until the last bit of data is shifted out. The last bit of data shifted is the LSB of the Q data from the channel. SDO is three-stated when the serial port is outside its time slot. This allows the AD6650 to share the SDIN of a DSP with other AD6650s or other devices. SDFS SDFS is the serial data frame sync signal ...
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... IF frequency that will be translated to dc. If enhanced performance is desired from the coarse dc correction switch or other device can be used to shut off the input of the AD6650 until the correction has been completed. Table 12. DC Correction Register Recommendations ...
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... The input resistance for the AD6650 is 200 Ω, and the input voltage range p-p differential. This equates to 4 dBm full-scale input power. The recommended method for driving the analog input of the AD6650 is to use an RF balun. C101 C102 J101 ...
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... To minimize capacitive loading, the number of gates on each output pin should be limited. The series resistors should be placed as close to the AD6650 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and the DVDD pin ...
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... SYNC pin (Pin_SYNC). The first sync event starts the device, and subsequent sync events resynchronize the filters of the AD6650. By using a start holdoff counter possible to align the phase of the AD6650 to other devices. To synchronize the AD6650 with external hardware, see the Start with SYNC Pin section. ...
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... Bit 5 to Bit 2 of the ACR register are instruction bits that allow multiple AD6650s to receive the same write access. The instruction bits allow a single or multiple (up to four) AD6650 chip( configured simultaneously. There are seven possible instructions that are defined in Table 14, where x represents disregarded values in the digital decoding ...
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... DR1, and Data Register DR0, respectively. All internal data- words have widths that are less than or equal to 22 bits. Access to DR0 triggers an internal access to the AD6650 based on the address indicated in ACR and CAR. Therefore, during writes to the internal registers, DR0 must be written last. At this point, data is transferred to the internal memory location indicated in A[9:0] ...
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... Test clock TMS Test access port mode select TDI Test data input TDO Test data output The AD6650 supports three op codes, listed in Table 17. These instructions set the mode of the JTAG interface. Table 17. Boundary Scan Op Codes Instruction Bypass Sample/Preload Extest A boundary scan description language (BSDL) file for this device is available ...
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... Bit 0 of the AutoCalibration control register is set high. Enables the PN sequence generator to test the digital block. Enables coarse DCC. This register must be held high during start-up sequence for coarse dc correction to occur. Rev Page AD6650 Additional Information Code Result 0 Bypass 1 Divide-by-2 ...
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... AD6650 Reg. Bit (Hex) Mnemonic Width B DC Correction Control 13: Upper 7 Threshold Lower Threshold Minimum Period 5 2: Bypass 1 1: Interpolate 1 0: Freeze 1 C AGC Control Force VGA Gain 1 2: FD_Enable 1 1: FA_Enable 1 0: Reserved 1 Description Fine DCC control registers. ...
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... The gain word does not change if the peak measurement falls between the upper and lower hysteresis threshold. The requested level for the slow loop. The full-scale input into the AD6650 p dBm. exponent Loop gain = (mantissa/256) × ½ . ...
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... AD6650 Reg. Bit (Hex) Mnemonic Width 10 AGC Control 10: FD_Step FA_Thresh FA_Count FA_Step 4 11 AGC Control SPB Peak 8 Detector Period Reserved 8 12 Reserved 7 13 AGC Control SPB Threshold Description Fast attack and fast decay loop parameters ...
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... CIC4 stage increments. This register has a range 20, which supports decimations from according to Equation 4. Sync mask. Decimation Phase from − 1. RCF Range taps. Rev Page AD6650 Additional Information Code Count ...
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... AD6650 Reg. Bit (Hex) Mnemonic Width 1B RCF Taps (N − Taps 1C RCF Scale 2 1D BIST for A BIST for A BIST for B BIST for B Serial Control 9 8: Fine DCC Data to BIST Data Serial Ouput 1 Select I_SDFS Control ...
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... Clock Divider Control [1] The clock divider control bit sets the internal clock rate for the AD6650. If this bit is set low and the clock rate is ≤52 MSPS, the internal divide-by-2 is bypassed faster clock rate is desired, the clock divider control bit should be set high. By setting this bit high, the internal divide-by-2 is used ...
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... AD6650 0x0A: Coarse DC Correction Control Register [3:0] Address 0xA is the coarse dc correction control register used to enable the coarse correction with Bit 0 and to initiate calibrations on Channel A and/or Channel B. Bit 3 and Bit 2 of this register can be used to initiate coarse calibrations when the device is running and can be used in conjunction with an external switch if desired ...
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... These two bits are reserved and should be written low. Bit 5 to Bit 0 This 6-bit register represents the loop gain mantissa for the slow loop of the AD6650 AGC. The values for this register range from 0 to 63. The equation for the loop gain is noted in the AGC Loop/Relinearization section. ...
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... Address 0x17 is the IIR control register. When this bit is set to 0, the sync mask is disabled. In this mode, after a SYNC is issued to the AD6650, the IIR data path is not cleared. If the sync mask is enabled, the bit is set to 1, and the data path is cleared of its contents and starts accumulating new data on the first valid clock after a Soft_SYNC or Pin_SYNC is issued ...
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... Bit 0 Enables the autocalibration. This should be set to 1 for the calibration to run automatically. Then the AD6650 waits approximately 20.63 ms after a Soft_SYNC or Pin_SYNC enables the part and then runs a coarse dc calibration. This allows some warm-up time for the analog path to thermally stabilize ...
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... AD6650BBCZ −25°C to +85°C AD6650/PCB 1 The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C to −40° Pb-free part. ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...